Allen and Holberg - CMOS Analog Circuit Design
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Allen and Holberg - CMOS Analog Circuit Design |
II.5-11 |
BIPOLARS IN CMOS TECHNOLOGY
Metal
Emitter (p+) |
Base (n+) |
FOX |
FOX |
FOX |
n- well |
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WB |
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Collector (p- substrate) |
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Figure 2.5-1 Substrate BJT available from a bulk CMOS process.
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Depletion regions |
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p |
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n |
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p |
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Emitter |
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Base |
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Collector |
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Carrier concentration |
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ppE |
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nn(x) |
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ppC |
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npE(0) |
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pn(0) |
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N |
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N |
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D |
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A |
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NA |
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npE |
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pn(x) |
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p |
n |
(w |
B |
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ppC |
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x |
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x=0 |
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x=wB |
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Figure 2.5-2 Minority carrier concentrations for a bipolar junction transistor.
Allen and Holberg - CMOS Analog Circuit Design |
II.6-1 |
II.6 - LATCHUP
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S |
G |
D=B |
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S |
G |
D=A |
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VDD |
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Substrate tie |
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Well tie |
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p+ |
FOX |
n+ |
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n+ |
FOX |
p+ |
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p+ |
FOX |
n+ |
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Q1 |
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Q2 |
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RN- |
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n-well |
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p-substrate |
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RP- |
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(a) |
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VDD |
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RN- |
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Q2 |
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A |
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Q1
B
RP-
(b)
Figure 2.5-3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS integrated circuits. (b) Equivalent circuit of the SCR formed from the parasitic bipolar transistors.
Allen and Holberg - CMOS Analog Circuit Design |
II.6-2 |
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PREVENTING LATCHUP |
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p-channel transistor |
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n-channel transistor |
n+ guard bars |
p+ guard bars |
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VDD |
VSS |
FOX n-well
p- substrate
Figure 2.5-4 Preventing latch-up using guard bars in an n-well technology
Allen and Holberg - CMOS Analog Circuit Design |
II.6-1 |
II.7 - ESD PROTECTION
VDD
p+ – n-well diode
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Bonding |
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To internal gates |
Pad |
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p+ resistor |
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n+ – substrate diode
VSS
(a)
Metal
n+
p-substrate
FOX
p+
n-well
FOX
(b)
Figure 2.5-5 Electrostatic discharge protection circuitry. (a) Electrical equivalent circuit (b) Implementation in CMOS technology
Allen and Holberg - CMOS Analog Circuit Design |
II.8-1 |
II.8 - GEOMETRICAL CONSIDERATIONS
Design Rules for a Double-Metal, Double-Polysilicon, N-Well, Bulk CMOS Process.
Minimum Dimension Resolution (λ)
1.N-Well
1A. |
width ......................................................................... |
6 |
1B. |
spacing .................................................................... |
12 |
2.Active Area (AA)
2A. |
width ......................................................................... |
4 |
Spacing to Well |
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2B. |
AA-n contained in n-Well............................................. |
1 |
2C. |
AA-n external to n-Well............................................. |
10 |
2D. |
AA-p contained in n-Well............................................. |
3 |
2E. |
AA-p external to n-Well............................................... |
4 |
Spacing to other AA (inside or outside well) |
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2F. |
AA to AA (p or n)....................................................... |
3 |
3.Polysilicon Gate (Capacitor bottom plate)
3A. |
width.......................................................................... |
2 |
3B. |
spacing ....................................................................... |
3 |
3C. |
spacing of polysilicon to AA (over field)........................ |
1 |
3D. |
extension of gate beyond AA (transistor width dir.) ........ |
2 |
3E. |
spacing of gate to edge of AA (transistor length dir.) ...... |
4 |
4.Polysilicon Capacitor top plate
4A. |
width.......................................................................... |
2 |
4B. |
spacing ....................................................................... |
2 |
4C. |
spacing to inside of polysilicon gate (bottom plate).......... |
2 |
5.Contacts
Allen and Holberg - CMOS Analog Circuit Design |
II.8-2 |
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5A. |
size ....................................................................... |
2x2 |
5B. |
spacing ....................................................................... |
4 |
5C. |
spacing to polysilicon gate ............................................ |
2 |
5D. |
spacing polysilicon contact to AA .................................. |
2 |
5E. |
metal overlap of contact ............................................... |
1 |
5F. |
AA overlap of contact .................................................. |
2 |
5G. |
polysilicon overlap of contact........................................ |
2 |
5H. |
capacitor top plate overlap of contact............................. |
2 |
6.Metal-1
6A. |
width.......................................................................... |
3 |
6B. |
spacing ....................................................................... |
3 |
7. Via |
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7A. |
size ....................................................................... |
3x3 |
7B. |
spacing ....................................................................... |
4 |
7C. |
enclosure by Metal-1.................................................... |
1 |
7D. |
enclosure by Metal-2.................................................... |
1 |
8.Metal-2
8A. |
width.......................................................................... |
4 |
8B. |
spacing ....................................................................... |
3 |
Bonding Pad |
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8C. |
spacing to AA............................................................ |
24 |
8D. |
spacing to metal circuitry ........................................... |
24 |
8E. |
spacing to polysilicon gate .......................................... |
24 |
Allen and Holberg - CMOS Analog Circuit Design |
II.8-3 |
9.Passivation Opening (Pad)
9A. |
bonding-pad opening .............................. |
100 m x 100 m |
9B. |
bonding-pad opening enclosed by Metal-2 ...................... |
8 |
9C. |
bonding-pad opening to pad opening space |
................... 40 |
Note: For a P-Well process, exchange p and n in all instances.
Allen and Holberg - CMOS Analog Circuit Design |
II.8-4 |
1B
1A
2E
2B |
2A |
2C |
2D |
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3C |
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3A |
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3E |
3D |
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3B
Figure 2.6-8(a) Illustration of the design rules 1-3 of Table 2.6-1.
Allen and Holberg - CMOS Analog Circuit Design |
II.8-5 |
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4C |
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4B |
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5C
5A
5B
5D
5E
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5F |
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5G |
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5H |
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Figure 2.6-8(b) |
Illustration of the design rules 4-5 of Table 2.6-1. |
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Allen and Holberg - CMOS Analog Circuit Design |
II.8-6 |
7A
6B
7C
6A
8A
8B
9B
9A
9C
N-WELL |
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N-AA |
POLYSILICON |
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POLYSILICON |
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CAPACITOR |
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GATE |
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METAL-2 |
PASSIVATION |
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7B
7D
P-AA
METAL-1
CONTACT VIA
Figure 2.6-8(c) Illustration of the design rules 6-9 of Table 2.6-1.