11. Minimization of excitation and output functions

Each function depends on 5 variables f(q1,q2,q3, x1,x2)

Karnaugh maps for implementing functions are presented in Fig. 16.

Fig. 16. Karnaugh maps for realized functions

Minimal cost implementation: the next state entries of the unused state are marked as “don’t-cares” (this simplifies the excitation logic).

J1 = q₂q₃x₁x₂; K1 = q₁;

J₂ = q₃x₂; K₂ = q₂x₁x₂;

J₃ = q₂x₁+q₂x₂; K₃ = q₃x₂;

y₁= q₂q₃x₁; y₂ = q₁q₃x_2;

7. Implementation the circuit of FSM in AND, OR, NOT basis.

Fig.16. The circuit of FSM using AND, OR, NOT gates.

Synchronizer

Digital systems of all types inevitably must deal with asynchronous input signals that are not synchronized with the system clock. A simple synchronizer is constructed based on the D-flip-flops, which sample the asynchronous inputs at each edge of the clock.

Fig.16. The structure of FSM with simple synchronizer

Implementation of the Circuit of fsm with Synchronizer on and, or, not Bases

S ynchronizer is implemented on the basis of two D-flip-flops: X1,X2 – asynchronous inputs, x1,x2 – synchronous input.

Fig. 17. The circuit of FSM with synchronizer

8. Description of FSM in Verilog

module Mealy_FSM(data_in,data_out,clk,reset);

input[1:0] data_in;

input clk,reset;

output[1:0] data_out;

reg[1:0] data_out;

reg[2:0] pres_state,next_state;

parameter s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100;

parameter A=2'b00, B=2'b01, C=2'b10;

//FSM Register

always @(posedge clk or negedge reset)

begin

if(!reset)

pres_state<=s0;

else pres_state<=next_state;

end

always @(pres_state or data_in)

case(pres_state)

s0: case(data_in)

A: next_state=s0;

B: next_state=s1;

C: next_state=s0;

default: next_state=s0;

endcase

s1: case(data_in)

A: next_state=s0;

B: next_state=s2;

C: next_state=s0;

default: next_state=s0;

endcase

s2: case(data_in)

A: next_state=s0;

B: next_state=s2;

C: next_state=s3;

default: next_state=s0;

endcase

s3: case(data_in)

A: next_state=s4;

B: next_state=s1;

C: next_state=s0;

default: next_state=s0;

endcase

s4: case(data_in)

A: next_state=s0;

B: next_state=s1;

C: next_state=s0;

default: next_state=s0;

endcase

default: next_state=s0;

endcase

always @(pres_state or data_in)

case(pres_state)

s2: case(data_in)

C: data_out=2'd2;

default: data_out=2'd0;

endcase

s4: case(data_in)

B: data_out=2'b01;

default: data_out=2'b00;

endcase

default: data_out=2'b00;

endcase

endmodule

module testbench;

parameter A=2'b00, B=2'b01, C=2'b10;

reg[1:0] data_in;

wire[1:0] data_out;

reg clk,reset;

Mealy_FSM my_mealy(data_in,data_out,clk,reset);