Приложение 2
module VGA (input clk, input start, input [3:0] R, input [3:0] G,
input [3:0] B, output [3:0] VGA_R, output [3:0] VGA_G, output [3:0] VGA_B,
output VGA_HS, output VGA_VS, output reg done, output reg givepix, output reg [9:0] state_ver, output reg f);
reg [10:0] cnt=11'b0;
reg [1:0] state_hor=2'b00;
reg HS=1'b1;
reg VS=1'b1;
reg [3:0] rR=4'b0000;
reg [3:0] rG=4'b0000;
reg [3:0] rB=4'b0000;
reg [1:0] delay=2'b00;
assign VGA_HS=HS;
assign VGA_VS=VS;
assign VGA_R=rR;
assign VGA_G=rG;
assign VGA_B=rB;
initial begin
done<=1'b1;
end
always @(posedge clk)
if (start)
begin
delay<=2'b00;
done<=1'b0;
cnt<=11'b0;
state_hor<=2'b00;
state_ver<=10'b0;
rR<=R;
rG<=G;
rB<=B;
HS<=1'b1;
VS<=1'b1;
f<=1'b0;
givepix<=1'b1;
end
else
if (!done)
case (state_hor)
2'b00:
begin
if (cnt<1270)
cnt<=cnt+1;
if (state_ver<480)
begin
if (f==1'b0)
f<=1'b1;
else
begin
f<=1'b0;
if (cnt<1269)
begin
rR<=R;
rG<=G;
rB<=B;
end
end
end
if (cnt==1270)
begin
cnt<=11'b0;
rR<=4'b0000;
rG<=4'b0000;
rB<=4'b0000;
givepix<=1'b0;
state_hor<=state_hor+1;
end
end
2'b01:
if (delay==2'b00)
begin
if (cnt<30)
cnt<=cnt+1;
if (cnt==30)
begin
cnt<=11'b0;
delay<=delay+1;
state_hor<=state_hor+1;
HS<=1'b0;
end
end
else
begin
if (cnt<31)
cnt<=cnt+1;
if (cnt==31)
begin
cnt<=11'b0;
if (delay<2'b11)
delay<=delay+1;
else
delay<=2'b00;
state_hor<=state_hor+1;
HS<=1'b0;
end
end
2'b10:
begin
if (cnt<190)
cnt<=cnt+1;
if (cnt==190)
begin
HS<=1'b1;
cnt<=11'b0;
state_hor<=state_hor+1;
end
end
2'b11:
begin
if (cnt<94)
cnt<=cnt+1;
if (cnt==94)
begin
if (state_ver<479)
begin
givepix<=1'b1;
rR<=R;
rG<=G;
rB<=B;
end
if (state_ver==489)
VS<=1'b0;
if (state_ver==491)
VS<=1'b1;
if (state_ver==524)
done<=1'b1;
cnt<=11'b0;
state_hor<=2'b00;
state_ver<=state_ver+1;
end
end
endcase
endmodule
Приложение 3
module i2c (input start, input clk50, input [8:0] data, input [6:0] addr, output I2C_SCLK, inout I2C_SDAT, output reg done, output reg [1:0] led);
reg sclk=1'b1;
reg sdat=1'b1;
reg [6:0] cnt=7'b0000000;
reg [2:0] state=3'b000;
reg [4:0] i=27;
reg err=1'b0;
wire [27:0] send={7'b0011010,1'b0,1'b1,addr,data[8],1'b1,data[7:0],1'b1,1'b0};
initial
done<=1'b1;
assign I2C_SCLK=sclk;
assign I2C_SDAT=((i!=18&i!=9&i!=0)|state!=3'b001)?sdat:1'bz;
always @(posedge clk50)
if (start)
begin
led<=3'b000;
sclk<=1'b1;
sdat<=1'b1;
cnt<=7'b0000000;
state<=3'b000;
i<=27;
done<=1'b0;
err<=1'b0;
end
else
if (!done)
case (state)
3'b000:
begin
if (cnt<29)
cnt<=cnt+1;
if (cnt==29)
begin
sdat<=1'b0;
cnt<=7'b0000000;
state<=state+1;
end
end
3'b001:
begin
if (cnt<34)
cnt<=cnt+1;
if (cnt==34)
begin
if (I2C_SDAT&(i==18|i==9|i==0))
begin
led[1]<=1'b1;
i<=0;
err<=1'b1;
end
state<=state+1;
sclk<=1'b0;
cnt<=7'b0000000;
end
end
3'b010:
begin
if (cnt<34) //t10=700 ns
cnt<=cnt+1;
if (cnt==34)
begin
sdat<=send[i];
cnt<=7'b0000000;
state<=state+1;
end
end
3'b011:
begin
if (cnt<29) //t5=600 ns
cnt<=cnt+1;
if (cnt==29)
begin
sclk<=1'b1;
cnt<=7'b0000000;
if (i>0)
begin
i<=i-1;
state<=3'b001;
end
if (i==0)
state<=state+1;
end
end
3'b100:
begin
if (cnt<29) //t8=600 ns
cnt<=cnt+1;
if (cnt==29)
begin
sdat<=1'b1;
if (err)
err<=1'b0;
else
begin
done<=1'b1;
led[0]<=1'b1;
end
i<=27;
state<=3'b000;
cnt<=7'b0000000;
end
end
endcase
endmodule