- •Navigating This Book
- •Table of Contents
- •Introduction
- •The History of Programmable Logic
- •Complex Programmable Logic Devices (CPLDs)
- •Why Use a CPLD?
- •Field Programmable Gate Arrays (FPGAs)
- •Design Integration
- •The Basic Design Process
- •HDL File Change Example
- •Before (16 x 16 multiplier):
- •After (32 x 32 multiplier):
- •Intellectual Property (IP) Cores
- •Design Verification
- •Xilinx Solutions
- •Introduction
- •Xilinx Devices
- •Platform FPGAs
- •Virtex FPGAs
- •Virtex-II Pro FPGAs
- •Virtex FPGAs
- •Spartan FPGAs
- •Spartan-3 FPGAs
- •Spartan-IIE FPGAs
- •Spartan-IIE Architectural Features
- •Xilinx CPLDs
- •XC9500 ISP CPLD Overview
- •XC9500XL 3.3V Family
- •XC9500XV 2.5V CPLD Family
- •CoolRunner Low-Power CPLDs
- •CoolRunner-II CPLDs
- •CoolRunner Reference Designs
- •Military and Aerospace
- •Automotive and Industrial
- •Design Tools
- •Design Entry
- •Synthesis
- •Implementation and Configuration
- •Board-Level Integration
- •Verification Technologies
- •Advanced Design Techniques
- •Embedded SW Design Tools Center
- •Xilinx IP Cores
- •Web-Based Information Guide
- •End Markets
- •Silicon Products and Solutions
- •Design Resources
- •System Resources
- •Xilinx Online (IRL)
- •Configuration Solutions
- •Processor Central
- •Tools and Partnerships
- •Memory Corner
- •Silicon
- •Design Tools and Boards
- •Technical Literature and Training
- •Connectivity Central
- •High-Speed Design Resources
- •Signal Integrity Tools
- •Partnerships
- •Signal Integrity
- •Services
- •Xilinx Design Services
- •Education Services
- •Live E-Learning Environment
- •Day Segment Courses
- •Computer-Based Training (CBT)
- •University Program
- •Design Consultants
- •Technical Support
- •Module Descriptions
- •WebPACK Design Suite
- •WebPACK Design Entry
- •WebPACK StateCAD
- •WebPACK MXE Simulator
- •WebPACK HDL Bencher Tool
- •WebPACK FPGA Implementation Tools
- •WebPACK CPLD Implementation Tools
- •WebPACK iMPACT Programmer
- •WebPACK ChipViewer
- •XPower
- •WebPACK CD-ROM Installation
- •Getting Started
- •Licenses
- •Projects
- •Summary
- •Introduction
- •Design Entry
- •The Language Template
- •Close the Language Templates
- •Edit the Counter Module
- •Save the Counter Module
- •Functional Simulation
- •State Machine Editor
- •Top-Level VHDL Designs
- •Top-Level Schematic Designs
- •ECS Hints
- •I/O Markers
- •Introduction
- •Synthesis
- •Constraints Editor
- •Implementing CPLDs
- •CPLD Reports
- •Timing Simulation
- •Configuration
- •Implementing FPGAs
- •Introduction
- •Synthesis
- •The Constraints File
- •FPGA Reports
- •Programming
- •Summary
- •Design Reference Bank
- •Introduction
- •Get the Most out of Microcontroller-Based Designs
- •Conventional Stepper Motor Control
- •Using a Microcontroller to Control a Stepper Motor
- •Stepper Motor Control Using a CPLD
- •PC-Based Motor Control
- •Design Partitioning
- •Conclusion
- •Documentation and Example Code
- •Website Reference
- •ACRONYMS
- •GLOSSARY OF TERMS
DESIGN REFERENCE BANK
Full-functioning software design tools for Xilinx CPLDs are free of charge and may be downloaded from the Xilinx website. Thus, your first project using CPLDs can be not only quick and painless, but very cost-effective as well.
(Excerpted from the Xilinx Xcell Journal, Issue 39, Spring 2001.)
Documentation and Example Code
The following is a list of selected application notes, white papers, tutorials, and example code that can be downloaded from the Xilinx website.
This list grows longer as more applications are developed. For the latest list, please visit www.xilinx.com/apps/appsweb.htm.
TABLE 7-1: DOCUMENTATION LIST
Title |
Number |
Family |
Design |
|
Code |
||||
|
|
|
||
|
|
|
|
|
Embedded Instrumentation |
XAPP076 |
XC9500 |
|
|
Using XC9500 CPLDs |
|
|
|
|
|
|
|
|
|
Configuring Xilinx FPGAs |
XAPP079 |
XC9500 |
|
|
Using an XC9500 CPLD and |
|
|
|
|
Parallel PROM |
|
|
|
|
|
|
|
|
|
Xilinx FPGAs: A Technical |
XAPP097 |
FPGA |
|
|
Overview for the First-Time |
|
|
|
|
User |
|
|
|
|
|
|
|
|
|
Choosing a Xilinx Product |
XAPP100 |
All |
|
|
Family |
|
|
|
|
|
|
|
|
|
XC9500 Remote Field Upgrade |
XAPP102 |
XC9500 |
|
|
|
|
|
|
|
A Quick JTAG ISP Checklist |
XAPP104 |
XC9500 |
|
|
|
|
|
|
|
A CPLD VHDL Introduction |
XAPP105 |
XC9500 |
|
|
|
|
|
|
|
Adapting ASIC Designs for |
XAPP119 |
Spartan |
|
|
Use with Spartan FPGAs |
|
|
|
|
|
|
|
|
|
170 MHz FIFOs using the |
XAPP131 |
Virtex |
|
|
Virtex Block SelectRAM+ |
|
|
|
|
Feature |
|
|
|
|
|
|
|
|
|
Synthesizable High- |
XAPP134 |
Virtex |
FREE |
|
Performance SDRAM |
|
|
VHDL |
|
Controllers |
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
• 173
PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK •
TABLE 7-1: DOCUMENTATION LIST (CONTINUED)
Title |
Number |
Family |
Design |
|
Code |
||||
|
|
|
||
|
|
|
|
|
Synthesizable 200 MHz ZBT |
XAPP136 |
Virtex |
FREE |
|
SRAM Interface |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
Virtex Synthesizable Delta- |
XAPP154 |
Virtex |
|
|
Sigma DAC v 1.1 |
|
|
|
|
|
|
|
|
|
MP3 NG: A Next Generation |
XAPP169 |
Spartan-II |
|
|
Consumer Platform |
|
|
|
|
|
|
|
|
|
Implementing an ISDN |
XAPP170 |
Spartan |
|
|
PCMCIA Modem Using |
|
|
|
|
Spartan Device, v1.0 |
|
|
|
|
|
|
|
|
|
Using Delay-Locked Loops in |
XAPP174 |
Spartan-II |
FREE |
|
Spartan-II FPGAs |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
High Speed FIFOs In Spartan-II |
XAPP175 |
Spartan-II |
FREE |
|
FPGAs |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
IDCT Implementation in Virtex |
XAPP208 |
Virtex |
FREE |
|
Devices for MPEG |
|
|
VHDL |
|
Applications, v 1.1 |
|
|
|
|
|
|
|
|
|
PicoBlaze 8-Bit Microcontroller |
XAPP213 |
Virtex and |
|
|
for Virtex Devices |
|
Spartan |
|
|
|
|
|
|
|
CoolRunner Visor Springboard |
XAPP357 |
CoolRunner |
|
|
LED Test v1.1 |
|
|
|
|
|
|
|
|
|
CoolRunner XPLA3 SMBus |
XAPP353 |
CoolRunner |
FREE |
|
Controller Implementation |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
CoolRunner CPLD3 CPLD |
XAPP349 |
CoolRunner |
FREE |
|
8051 Microcontroller Interface |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
• 174
DESIGN REFERENCE BANK
TABLE 7-1: DOCUMENTATION LIST (CONTINUED)
Title |
Number |
Family |
Design |
|
Code |
||||
|
|
|
||
|
|
|
|
|
CoolRunner Serial Peripheral |
XAPP348 |
CoolRunner |
FREE |
|
Interface Master v1.2 |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
UARTs in Xilinx CPLDs |
XAPP341 |
CoolRunner |
FREE |
|
|
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
Design of a 16b/20b |
XAPP336 |
CoolRunner |
FREE |
|
Encoder/Decoder Using a |
|
|
VHDL |
|
CoolRunner XPLA3 CPLD |
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
CoolRunner CPLD I2C Bus |
XAPP333 |
CoolRunner |
FREE |
|
Controller Implementation |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
Manchester Encoder-Decoder |
XAPP339 |
CoolRunner |
FREE |
|
for Xilinx CPLDs v1.3 |
|
|
VHDL |
|
|
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
Design of a MP3 Portable |
XAPP328 |
CoolRunner |
FREE |
|
Player Using a CoolRunner |
|
|
VHDL |
|
CPLD |
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
|
Content Addressable Memory |
XAPP202 |
Virtex, Virtex- |
FREE |
|
(CAM) |
|
II |
VHDL |
|
in ATM Applications |
|
|
and |
|
|
|
Verilog |
||
|
|
|
||
|
|
|
|
|
Virtex Analog to Digital |
XAPP155 |
Virtex |
|
|
Converter v1.1 |
|
|
|
|
|
|
|
|
|
Design an Eight Channel |
XAPP146 |
CoolRunner |
FREE |
|
Digital Volt Meter with a |
|
|
VHDL |
|
Springboard Development Kit |
|
|
and |
|
|
|
|
Verilog |
|
|
|
|
|
• 175
PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK •
TABLE 7-1: DOCUMENTATION LIST (CONTINUED)
Title |
Number |
Family |
Design |
|
Code |
||||
|
|
|
||
|
|
|
|
|
Exemplar/ModelSim Tutorial |
Tutorial |
CPLDs |
|
|
for CPLDs |
|
|
|
|
|
|
|
|
|
Workstation Flow for Xilinx |
Tutorial |
CPLDs |
|
|
CoolRunner CPLDs |
|
|
|
|
|
|
|
|
|
OrCAD/ModelSim Tutorial for |
Tutorial |
CPLDs |
|
|
CPLDs |
|
|
|
|
|
|
|
|
|
Understanding the |
XAPP375 |
CoolRunner-II |
|
|
CoolRunner-II Timing Model |
|
|
|
|
|
|
|
|
|
Understanding the |
XAPP376 |
CoolRunner-II |
|
|
CoolRunner-II Logic Engine |
|
|
|
|
|
|
|
|
|
Using CoolRunner-II |
XAPP378 |
CoolRunner-II |
FREE |
|
Advanced Features |
|
|
HDL |
|
|
|
|
|
|
High Speed Design with |
XAPP379 |
CoolRunner-II |
|
|
CoolRunner-II CPLDs |
|
|
|
|
|
|
|
|
|
Powering CoolRunner-II |
XAPP389 |
CoolRunner-II |
|
|
CPLDs |
|
|
|
|
|
|
|
|
|
Low Power Design with |
XAPP377 |
CoolRunner-II |
|
|
CoolRunner-II CPLDs |
|
|
|
|
|
|
|
|
|
Title |
Number |
Family |
Design |
|
|
|
|
Code |
|
|
|
|
|
|
CoolRunner-II I/O |
XAPP382 |
CoolRunner-II |
|
|
Characteristics |
|
|
|
|
|
|
|
|
|
5V Tolerance Techniques for |
XAPP429 |
CoolRunner-II |
|
|
CoolRunner-II Devices |
|
|
|
|
|
|
|
|
|
Building Crosspoint Switches |
XAPP380 |
CoolRunner-II |
FREE |
|
with CoolRunner-II CPLD |
|
|
HDL |
|
|
|
|
|
|
Telematics Digital |
WP194 |
All Products |
|
|
Convergence – How to Cope |
|
|
|
|
with Emerging Standards and |
|
|
|
|
Protocols |
|
|
|
|
|
|
|
|
|
CipherStream Protocol: How |
WP197 |
CoolRunner-II |
|
|
CoolRunner-II CPLDs Protect |
|
|
|
|
FPGA IP v1.0 |
|
|
|
|
|
|
|
|
• 176
