Philips Semiconductors |
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Product specification |
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48 × 84 pixels matrix LCD controller/driver |
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PCD8544 |
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9 LIMITING VALUES |
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In accordance with the Absolute Maximum Rating System (IEC 134); see notes 1 and 2. |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
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UNIT |
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VDD |
supply voltage |
note 3 |
−0.5 |
+7 |
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V |
VLCD |
supply voltage LCD |
note 4 |
−0.5 |
+10 |
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V |
Vi |
all input voltages |
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−0.5 |
VDD + 0.5 |
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V |
ISS |
ground supply current |
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−50 |
+50 |
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mA |
II, IO |
DC input or output current |
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−10 |
+10 |
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mA |
Ptot |
total power dissipation |
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− |
300 |
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mW |
PO |
power dissipation per output |
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− |
30 |
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mW |
Tamb |
operating ambient temperature |
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−25 |
+70 |
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°C |
Tj |
operating junction temperature |
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−65 |
+150 |
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°C |
Tstg |
storage temperature |
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−65 |
+150 |
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°C |
Notes
1.Stresses above those listed under limiting values may cause permanent damage to the device.
2.Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
3.With external LCD supply voltage externally supplied (voltage generator disabled). VDDmax = 5 V if LCD supply voltage is internally generated (voltage generator enabled).
4.When setting VLCD by software, take care not to set a VOP that will exceed the maximum of 8.5 V when operating at −25 °C, see Caution in Section 8.9.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
1999 Apr 12 |
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Philips Semiconductors |
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Product specification |
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48 × 84 pixels matrix LCD controller/driver |
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PCD8544 |
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11 DC CHARACTERISTICS |
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VDD = 2.7 to 3.3 V; VSS = 0 V; VLCD = 6.0 to 9.0 V; Tamb = −25 to +70 °C; unless otherwise specified. |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VDD1 |
supply voltage 1 |
LCD voltage externally |
2.7 |
− |
3.3 |
V |
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supplied (voltage generator |
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disabled) |
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VDD2 |
supply voltage 2 |
LCD voltage internally |
2.7 |
− |
3.3 |
V |
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generated (voltage |
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generator enabled) |
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VLCD1 |
LCD supply voltage |
LCD voltage externally |
6.0 |
− |
9.0 |
V |
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supplied (voltage generator |
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disabled) |
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VLCD2 |
LCD supply voltage |
LCD voltage internally |
6.0 |
− |
8.5 |
V |
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generated (voltage |
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generator enabled); note 1 |
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IDD1 |
supply current 1 (normal mode) |
VDD = 2.85 V; VLCD = 7.0 V; |
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240 |
300 |
μA |
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for internal VLCD |
fSCLK = 0; Tamb = 25 °C; |
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display load = 10 μA; note 2 |
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IDD2 |
supply current 2 (normal mode) |
VDD = 2.70 V; VLCD = 7.0 V; |
− |
− |
320 |
μA |
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for internal VLCD |
fSCLK = 0; Tamb = 25 °C; |
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display load = 10 μA; note 2 |
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IDD3 |
supply current 3 (Power-down |
with internal or external LCD |
− |
1.5 |
− |
μA |
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mode) |
supply voltage; note 3 |
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IDD4 |
supply current external VLCD |
VDD = 2.85 V; VLCD = 9.0 V; |
− |
25 |
− |
μA |
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fSCLK = 0; notes 2 and 4 |
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ILCD |
supply current external VLCD |
VDD = 2.7 V; VLCD = 7.0 V; |
− |
42 |
− |
μA |
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fSCLK = 0; T = 25 °C; |
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display load = 10 μA; |
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notes 2 and 4 |
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Logic |
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VIL |
LOW level input voltage |
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VSS |
− |
0.3VDD |
V |
VIH |
HIGH level input voltage |
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0.7VDD |
− |
VDD |
V |
IL |
leakage current |
VI = VDD or VSS |
−1 |
− |
+1 |
μA |
Column and row outputs |
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Ro(C) |
column output resistance |
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− |
12 |
20 |
kΩ |
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C0 to C83 |
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Ro(R) |
row output resistance R0 to R47 |
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− |
12 |
20 |
kΩ |
Vbias(tol) |
bias voltage tolerance on |
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−100 |
0 |
+100 |
mV |
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C0 to C83 and R0 to R47 |
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1999 Apr 12 |
18 |
Philips Semiconductors |
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Product specification |
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48 × 84 pixels matrix LCD controller/driver |
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PCD8544 |
|||
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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LCD supply voltage generator |
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VLCD |
VLCD tolerance internally |
VDD = 2.85 V; VLCD = 7.0 V; |
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0 |
300 |
mV |
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generated |
fSCLK = 0; |
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display load = 10 μA; note 5 |
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TC0 |
VLCD temperature coefficient 0 |
VDD = 2.85 V; VLCD = 7.0 V; |
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1 |
− |
mV/K |
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fSCLK = 0; |
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display load = 10 μA |
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TC1 |
VLCD temperature coefficient 1 |
VDD = 2.85 V; VLCD = 7.0 V; |
− |
9 |
− |
mV/K |
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fSCLK = 0; |
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display load = 10 μA |
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TC2 |
VLCD temperature coefficient 2 |
VDD = 2.85 V; VLCD = 7.0 V; |
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17 |
− |
mV/K |
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fSCLK = 0; |
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display load = 10 μA |
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TC3 |
VLCD temperature coefficient 3 |
VDD = 2.85 V; VLCD = 7.0 V; |
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24 |
− |
mV/K |
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fSCLK = 0; |
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display load = 10 μA |
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Notes |
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1.The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load.
2.Internal clock.
3.RAM contents equal ‘0’. During power-down, all static currents are switched off.
4.If external VLCD, the display load current is not transmitted to IDD.
5.Tolerance depends on the temperature (typically zero at 27 °C, maximum tolerance values are measured at the temperate range limit).
1999 Apr 12 |
19 |