Chapter 1

Introduction

This chapter describes the architecture of the AXI protocol and the basic transactions that the protocol defines. It contains the following sections:

•About the AXI protocol on page 1-2

•Architecture on page 1-3

•Basic transactions on page 1-7

•Additional features on page 1-11.

Introduction

1.1About the AXI protocol

The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for a high-speed submicron interconnect.

The objectives of the latest generation AMBA interface are to:

•be suitable for high-bandwidth and low-latency designs

•enable high-frequency operation without using complex bridges

•meet the interface requirements of a wide range of components

•be suitable for memory controllers with high initial access latency

•provide flexibility in the implementation of interconnect architectures

•be backward-compatible with existing AHB and APB interfaces.

The key features of the AXI protocol are:

•separate address/control and data phases

•support for unaligned data transfers using byte strobes

•burst-based transactions with only start address issued

•separate read and write data channels to enable low-cost Direct Memory Access (DMA)

•ability to issue multiple outstanding addresses

•out-of-order transaction completion

•easy addition of register stages to provide timing closure.

As well as the data transfer protocol, the AXI protocol includes optional extensions that cover signaling for low-power operation.