Questions for Self-Testing

1. What kind of means allows using the Power-3 in SMP-systems?

2. What is the structure of the Power-3 microprocessor?

3. What are the peculiarities of the Power-4 structure?

4. What stages does the Power-4 conveyer have?

5. What structure does the 4-processor cluster-system based on Роwеr 4 have?

6. How to split the eight basic renaming alternatives into 16 feasible implementation schemes?

7. Why do relevant superscalar processors use only four of the eight possible basic alternatives of renaming?

8. What is the technology of register renaming used for?

9. What is the role of the reorder buffer (ROB) in the renaming technology?

10. What is the essence of the method of register mapping?

6.4. Microarchitecture Level Power-Performance Fundamentals

At the elementary transistor gate level, we can formulate total power dissipation as the sum of three major components: switching loss, leakage, and short-circuit loss.

PW_device = (1/2)C V_DD V_swing af + I_leakage V_DD + I_sc V_DD (6.1)

Here, C is the output capacitance, V_DD is the supply voltage, f is the chip clock frequency, and a is the activity factor (0<a<1) that determines the device switching frequency. V_swing is the voltage swing across the output capacitor. I_leakage is the leakage current, and I_sc is the average short-circuits current.

The literature often approximates V_swing as equal to V_DD (or simply V for short), making the switching loss around (1/2)CV²af. Also for current ranges of V_DD (say, 1 volt to 3 volts) switching loss, (1/2)CV²af remains the dominant component. So as a first-order approximation for the whole chip we may formulate the power dissipation as

PW_chip = (6.2)

C_i, V_i, a_i, and f_i are unit- or block-specific average values. The summation is taken overall blocks or units i, at the microarchitecture level (instruction cache, data cache, integer unit; floating-point unit, load-store unit, register files, and buses). For the voltage range considered, the operating frequency is roughly proportional to the supply voltage; C remains roughly the same if we keep the same design, but scale the voltage. If a single voltage and clock frequency is used for the whole chip, the formula reduces to

(6.3)

where K's are unit- or block-specific constants. If we consider the worst case activity factor for each unit i – that is, if a_i=1 for all i, then

PW_chip=K_vV³=K_f f ³ (6.4)

where K_v and K_f are design-specific constants, where K's are unit- or block-specific constants.

That equation leads to the so-called cube-root rule. This point to the single most efficient method for reducing power dissipation for a processor designed to operate at high frequency: reduce the voltage (and hence the frequency). This is the primary mechanism of power control in Transmeta's Crusoe chip. There's a limit, however, on how much V_DD can be reduced (for a given technology), which has to do with manufacturability and circuit reliability issues. Thus, a combination of microarchitecture and circuit techniques to reduce power consumption – without necessarily employing multiple or variable supply voltages – is of special relevance.

Performance Basics. The most straightforward metric for measuring performance is the execution time of a representative workload mix on the target processor. We can write the execution time as

T =PL CPI CT =PL CPI (1/f ) (6.5)

Here, PL is the dynamic path length of the program mix, measured as the number of machine instructions executed. CPI is the average processor cycles per instruction incurred in executing the program mix, and CT is the processor cycle time (measured in seconds per cycle) whose inverse determines clock frequency f. Since performance increases with decreasing T, we may formulate performance PF as

PF_chip=K_pf f = K_pvV (6.6)

Here, the K's are constants for a given microarchitecture-compiler implementation. The K_pf value stands for the average number of machine instructions executed per cycle on the machine being measured. PF_chip in this case is measured in MIPS.

Adopting a noncontroversial weighted mix is not easy. Each ratio is calculated as the speedup with respect to execution time on a specified reference machine. This method has the advantage of allowing us to rank different machines unambiguously from a performance viewpoint. That is, we can show the ranking as independent of the reference machine used in such a formulation.

SMT/CMP Differences and Energy-Efficiency Issues. Consider the floating-point loop kernel shown in Table 6.1.

Table 6.1.

Example loop test case

Parallel instruction tags	Instruction	Load/store instruction	Description
T	A	fadd fp3, fp1, fp0	; add FPR fp1 and fp0; store into target register fp3
U	B	lfdu fp5, 8(r1)	; load FPR fp5 from memory address: 8 + contents of GPR r1
V	C	lfdu fp4, 8(r3)	; load FPR fp4 from memory address: 8 + contents of GPR r3
W	D	fadd fp4, fp5, fp4	; add FPR fp5 and fp4; store into target register fp4
X	E	fadd fp1, fp4, fp3	; add FPR fp4 and fp3; store into target register fp1
Y	F	stfdu fp1, 8(r2)	; store FPR fp1 to memory address: 8 + contents of GPR r2
Z	G	bc loop_yop	; branch back conditionally to top of loop body

The loop body consists of seven instructions labeled A through G. The final instruction is a conditional branch that causes control to loop back to the top of the loop body. Labels T through Z are used to tag the corresponding instructions for a parallel thread when considering SMT and CMP. The lfdu/stfdu instructions are load/store instructions with update where the base address register (say, r1, r2, or r3) is updated to hold the newly computed address. We assumed that the base machine is a four-wide superscalar processor with two load-store units supporting two floating-point pipes. The data cache has two load ports and a separate store port. The two load-store units (LSU0 and LSU1) are fed by a single issue queue LS0; similarly, the two floating-point units (FPU0 and FPU1) are fed by a single issue queue FPQ. In the context of the loop just shown, we essentially focus on the LSU-FPU subengine of the whole processor.

Assume that the following high-level parameters (latency and bandwidth) characterizing the base superscalar machine:

• Instruction fetch bandwidth fetch_bw of two times W is eight instructions per cycle.

• Dispatch/decode/rename bandwidth equals W, which is four instructions/cycle; dispatch stalls beyond the first branch scanned in the instruction fetch buffer.

• Issue bandwidth from LSQ (reservation station) lsu_bw of W/2 is two instructions/cycle.

• Issue bandwidth from FPQ fpu_bw of W/2 is two instructions/cycle.

• Completion bandwidth compl_bw of W is four instructions/cycle.

• Back-to-back dependent floating-point operation issue delay fp_delay is one cycle.

• The best-case load latency from fetch to write back is five cycles.

• The best-case store latency, from fetch to writing in the pending store queue is four cycles. (A store is eligible to complete the cycle after the address-data pair is valid in the store queue.)

• The best-case floating-point operation latency from fetch to write back is seven cycles (when the FPQ issue queue is bypassed because it's empty).

Load and floating-point operations are eligible for completion (retirement) the cycle after write back to rename buffers. For simplicity of analysis assume that the processor uses in-order issue from issue queues LSQ and FPQ. In our simulation model, superscalar width W is a ganged parameter, defined as follows:

• W= (fetch_bw/2) = disp_bw = compl_bw.

• The number of LSD units, Is_units, FPL units, fp_units, data cache load ports, I_ports, and data cache store ports, the term s_ports, vary as follows as W is changed: Is_units = fp_units = I_ports = max [floor(W/2), 1 ]. s_ports = max [floor(I_ports/2), 1 ].

We assumed a simple analytical energy model in which the power consumed is a function of parameters W, Is_units, fp_units, I_ports, and s_ports. In particular, the power (PW) in pseudowatts is computed as

PW = W ^0.5 + Is_units + fp_units + I_ports + s_ports.

Fig. 6.10 shows the performance and performance/power ratio variation with superscalar width. The MIPS values are computed from the CPI values, assuming a 1-GHz clock frequency.

T he graph in Fig. 6.10,a shows that a maximum issue width of four could be used to achieve the best (idealized) CPI performance. However as shown in Fig. 6.10,b, from a power-performance efficiency viewpoint (measured as a performance over power ratio in this example), the best-case design is achieved for a width of three. Depending on the sophistication and accuracy of the energy model (that is, how power varies with microarchitectural complexity) and the exact choice of the power-performance efficiency metric, the maximum value point in the curve in Fig. 6.10,b will change. However beyond a certain superscalar width, the power-performance efficiency will diminish continuously. Fundamentally, this is due to the single-thread ILP limit of the loop trace.

Note that the resource sizes (number of rename buffers, reorder buffer size, sizes of various other queues, caches, and so on) are assumed to be large enough that they're effectively infinite for the purposes of our running example. Some of the actual sizes assumed for the base case (W = 4) are

• completion (reorder) buffer size cbuf_size of 32,

• load-store queue size lsq_ of 6,

• floating-point queue fpqze of 8, and

• pending store queue size psq_size of 16.

The microarchitectural trends beyond the current superscalar regime are effectively targeted toward the goal of extending the processing efficiency factors. That is, the complexity growth must ideally scale at a slower rate than performance growth. Power consumption is one index of complexity; it also determines packaging and cooling costs. (Verification cost and effort is another important index.) In that sense, striving to ensure that the power-performance efficiency metric of choice is a nondecreasing function of time is a way of achieving complexity-effective designs.

In a multiscalar-type CMP machine, different iterations of a loop program could be initiated as separate tasks or threads on different core processors on the same chip. Thus in a two-way multiscalar CMP, a global task sequencer would issue threads A-B-C-D-E-F-G and T-U-V-W-X-Y-Z derived from the same user program in sequence to two cores.

Register values set in one task are forwarded in sequence to dependent instructions in subsequent tasks. For example, the register value in fp1 set by instruction E in task 1 must be communicated to instruction T in task 2. So instruction T must stall in the second processor until the value communication has occurred from task 1. Execution on each processor proceeds speculatively, assuming the absence of load-store address conflicts between tasks. Dynamic memory address disambiguation hardware is required to detect violations and restart task executions as needed. If the performance can be shown to scale well with the number of tasks, and if each processor is designed as a limited-issue, limited-speculation (low-complexity) core, we can achieve better overall scalability of power-performance efficiency.