Questions for Self-Testing

1. How is the input and output gating for one-bit register carried out?

2. What is the structure of the open-collector bus?

3. What are the functions of the bus?

4. How is the timing of data transfers inside the CPU done?

5. What defines the minimum duration of the signal?

1.4. Computer Interface Organization

Presently there are a few standards of buses: ISA (Industry Standard Architecture), MCA (MicroChannel Architecture), EISA (Extended ISA), VESA (Video Electronics Standard Association), PCI (Peripheral Component Interconnect), AGP (Accelerated Graphics Port), SCSI (Small Computer System Interface), IEEE-1394 (FireWire), USB (Universal Serial Bus), etc.

The single-bus organization of Fig. 1.3 represents only one of the possibilities for interconnecting different building blocks of the CPU. An alternative arrangement is the two-bus structure shown in Fig. 1.8. All registers outputs are connected to bus A, and all register inputs are connected to bus B. The two buses are connected through the bus tie G, which, when enabled, transfers the data on bus A to bus B. When G is disabled, the two buses are electrically isolated. Note that the temporary storage register Z in Fig. 1.3 is not required in this organization because, with the bus tie disabled, the output of the ALU can be transferred directly to the destination register. For example, the addition operation discussed earlier (R3 ← [R1] + [R2]) can now be performed as follows:

Step	Action
1	R1out, Genable, Yin
2	R2out, Add, ALUout, R3in

It is important to note that if the registers are simple latches as in Fig. 1.5, the destination register in the above sequence should be different from R2, because the two operations R2_in and R2_out cannot be performed at the same time. This is because the ALU is a combinational network. Hence it has no internal storage. The operation R2 ← [R1] + [R2] can still be performed, however, by interchanging R1_out and R2_out and replacing R3_in by R2_in in step 2. The restriction that R2_out and R2_in cannot be performed in the same step may be relaxed through the use of edge-triggered flip-flops.

A ssuming that edge-triggered flip-flops are used, the timing of a register transfer involving R2 remains essentially the same as that of Fig. 1.7, with Z_in replaced by R2_in. In this case, R2_in represents the clock input to the register, which is assumed to be negative edge-triggered. The output of R2 remains unchanged until t₂, at which time the data available on the input bus is loaded into R2.

Let us consider one more example of a CPU organization. Fig. 1.9 illustrates three-bus architecture, with each bus connected to only one output and a number of inputs. The elimination of the need for connecting more than one output to the same bus leads to faster bus transfers and simpler control. A multiplexer is provided at the input to each of the two work registers A and B, which allows them to be loaded from either the input data bus or the register data bus. The general-purpose registers of the CPU in Fig. 1.9 are shown as a single block. They are assumed to be implemented using RAM.

Graphics-oriented operating systems have created a data bottleneck between the processor and its display peripherals in standard PC I/O architectures. Moving peripheral functions with high bandwidth requirements closer to the system's processor bus can eliminate this bottleneck. Substantial performance gains are seen with graphical user interfaces (GUIs) and other high bandwidth functions when a "local bus" design is used.

The advantages offered by local Bus designs have motivated several versions of local bus implementations. The benefits of establishing an open standard for system I/O buses have been clearly demonstrated in the PC industry. It is important that a new standard for local buses be established to simplify designs, reduce costs, and increase the selection of local bus components and add-in cards.

P eripheral Component Interconnect Local Bus. The Peripheral Component Interconnect (PCI) Bus has been defined with the primary goal of establishing an industry standard, high performance local bus architecture that offers low cost and allows differentiation. While the primary focus is on enabling new price-performance points in today's systems, it is important that a new standard also accommodates future system requirements and be applicable across multiple platforms and architectures. Fig. 1.10 shows the multiple dimensions of the PCI Local Bus. While the initial focus of local bus applications has been on low to high-end desktop systems, the PCI Local Bus also comprehends the requirements from mobile applications up through departmental servers. The 3.3-volt requirements of the mobile environment and the imminent move from 5 volts to 3.3 volts in desktop applications must be accounted for in a new standard. The PCI Local Bus specifies both voltages and describes a clear migration path between them. The PCI component and add-in card interface is processor independent, enabling an efficient transition to future processor generations and use with multiple processor architectures. Processor independence allows the PCI Local bus to be organized for I/O functions, enables concurrent operation of the local bus with the processor/memory subsystem, and accommodates multiple high performance peripherals in addition to graphics (Video, SCSI, etc). Movement to enhanced video and multimedia displays and other high bandwidth I/O will continue to increase local bus bandwidth requirement [55], [56], [61], [62].

A transparent 64-bit extension of the 32-bit data and address buses is defined, doubling the bus bandwidth and offering forward and backwards compatibility of 32-bit and 64-bit PCI Local Bus peripherals. The PCI Local Bus standard offers additional benefits to the users of PCI based systems. Configuration registers are specified for PCI components and add-in cards. A system with embedded auto configuration software offers true ease-of-use for the system user by automatically configuring PCI add-in cards at power on.

The block diagram (Fig. 1.11) shows a typical PCI Local bus system architecture. This example is not intended to imply any specific architectural limits. In this example, the processor/cache/memory subsystem is connected to PCI through a PCI bridge. This bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address spaces. It also provides a high bandwidth path allowing PCI masters direct access to main memory. The bridge may optionally include, such functions as data buffering/posting and PCI-central functions (e.g., arbitration). Typical PCI Local Bus implementations will support up to three add-in board connectors, although expansion capability is not required.

PCI expansion cards use an edge connector and motherboards that allow a female connector to be mounted parallel to the system bus connectors. To provide a quick and easy transition from 5V to 3.3V component technology, PCI defines two add-in board connectors: one for the 5V signaling environment and one for the 3.3V signaling environment. Two sizes of PCI add-in boards are defined: standard length and short length. Systems are not required to support both board types. The standard boards include an ISA/EISA extender to enable them to use ISA/EISA card guides in ISA/EISA systems. To accommodate the 5V and 3.3V signaling environments and to facilitate a smooth migration path between the voltages, three add-in board electrical types are specified: a "5 volt" board which plugs into only the 5V connector, a "universal" board which plugs into both 5V and 3.3V connectors, and a "3.3 volt" board which plugs into only the 3.3V connector. Two types of PCI backplates are currently defined: ISA/EISA- and MCA-compatible. The interchangeable backplates must both be supplied with each PCI Local Bus add-in board shipped to accommodate usage of the board in all three-system types. It is assumed that typical low bandwidth; after-market add-ins will remain on the standard I/O expansion buses such as ISA, EISA, or MC. One component (or set of components) on PCI may generate the standard I/O expansion bus used in the system. In some mobile or client systems, a standard expansion bus may not be required. The PCI Local Bus was specified to establish a high performance local bus standard for several generations of product. The PCI specification provides a selection of features that can achieve multiple price-performance points and can enable functions that allow differential at the system and component level.

The Small Computer Systems Interface (SCSI) bus width is either 8 bits or 16 bits. The SCSI bus may also be either Single ended or Differential; however the two are mutually exclusive. SCSI is a chained parallel bus; cables start at the Host and run from device to device in a chain. SCSI may be used for asynchronous and synchronous transfers; Asynchronous transfers using Start and Stop bits and synchronous transfers using system timing (Hand-Shaking). The data bus also carries one parity bit. SCSI uses a 32 bit CRC-32, the 32-bit polynomial is X³²+ X²⁶+ X²³+ X²²+ X¹⁶+ X¹²+ X¹¹+ X¹⁰+ X⁸+ X⁷+ X⁵+ X⁴+ X²+ X +1. (CRC is Cyclic Redundancy Check and the mentioned polynomial is used for computing the parity bit).

Universal Serial Bus Interface. The USB (Universal Serial Bus) spec defines the Mechanical, Electrical and Protocol layers of the interface. Cables and connectors are fully defined. USB defines 2 types of hardware, Hubs and Functions. Up to 127 devices may be connected together in a tiered Star topology. The limiting factor is 7 address bits. The physical wire segments are point-to-point between a Host, Hub, or Function. The system may only have one Host, which connects to a Hub. A USB Hub may connect to another Hub or to a USB Function. Each layer transition from Hub to Hub represents another Tier. USB Hubs allow connection to a USB bus, while USB Functions are the devices which perform some function. The USB bus is a Differential Bi-directional serial interface cable bus. Differential nonreturn-to-zero (NRZI) data is transmitted Isochronous or Asynchronous between devices. Data is transferred at three different rates over a maximum cable length of 4 meters ~ over 4 wires, 2 of which carry data on a balanced twisted pair. USB may operate at any speed from 10kbps to 400Mbps in one of three speed modes. A Slow-Speed mode of 10kbps to 100kbps is used for devices such as a USB keyboard or USB mouse. Full-Speed mode is used by most devices and allows a transfer rate of 500kbps to 10Mbps. High-Speed mode (defined by USB 2.0) allows rates of up to 480Mbps, with a speed range of 25Mbps to 400Mbps.

Four different (packet) protocols are used; Control, Interrupt Isochronous and Bulk. Each exchange contains 3 packets; A token packet which holds the address, a data packet which holds the data, and a handshake packet which terminate the exchange. NRZI produces a change in the signal indicating a logic zero, no change indicates a logic one. Bit stuffing is used with NRZI to stop the signal remaining in the steady state condition; if more then 6 ones are transmitted (no change in the signal) a zero is inserted to produce a transition. NRZI, with bit stuffing is self clocking, allowing the receiver to synchronize with the transmitter.