- •1 Combination Circuits
- •1.1 Circuitry ttl-elements with Shottky diodes
- •Levels of Integration
- •Typical Set of ttl iCs
- •Transistor-transistor logic (ttl)
- •1.2 Element with the open collector Open-collector outputs
- •Tristate outputs
- •1.3 Emitter-coupled logic (ecl)
- •Emitter-coupled multivibrator
- •Emitter-coupled Schmitt trigger
- •1.4 Decoder
- •Priority decoder
- •Binary Decoders
- •Decoder Networks
- •1.5 Coder units Encoder Networks
- •Binary Encoders
- •Priority Encoders
- •1.6 Multiplexers (Selectors)
- •1.7 Multiplexer Trees
- •Demultiplexer Networks
- •Encoder Networks
- •1.8 Demultiplexers (Distributors)
- •1.9 Applicanion of multiplexer
- •1.10 Code converters
- •1.11 Shifters
- •Shifter Networks
- •Barrel Shifter
- •1.12 Comparators
- •Window comparator
- •Digital comparators
- •2 Sequentional Circuits
- •2.1 Circuritry of flips
- •Sequential logic systems
- •Integrated flip-flops
- •Transparent flip-flops
- •Clocked rs flip-flop
- •Clocked d flip-flop
- •Flip-flops with intermediate storage
- •2.2 Flips types Single-edge-triggered flip-flops
- •2.3 Statik registers
- •2.4 Shift register Combinatorial shift register (barrel shifter)
- •Shift Registers
- •2.5 Counters
- •Asynchronous straight binary counter
- •Counters
- •Ripple Counters
- •Asynchronous bcd counter
- •2.6 Synchronous reversal counters
- •Synchronous straight binary counters
- •Synchronous bcd counter
- •Synchronous one-shot
- •Synchronous edge detector
- •Synchronous clock switch
- •2.7 Schmitt flip-flops Schmitt trigger
- •Inverting Schmitt trigger
- •Precision Schmitt trigger
- •3 Memory Devices
- •3.1 Circuitri of memori element Semiconductor memories
- •3.2 Mask-type lic of the rom
- •RaMs as shift registers
- •First-In-First-Out Memories (fifOs)
- •Fifo implementation using standard raMs
- •Error detection and correction
- •Parity bit
- •Hamming code
- •3.3 Rom with singl programming Read-only memories (roMs)
- •Mask-programmed roMs (mroMs)
- •Programmable roMs (proMs)
- •3.4 Memori element with electrical erase Electrically erasable proMs (eeproMs)
- •3.5 Static ram
- •Timing considerations
- •3.6 Dynamic raMs
- •Dynamic ram controllers
- •3.7 Devices programmed
- •Programmable logic array (pal)
1.7 Multiplexer Trees
A 2n-input multiplexer can be implemented by a two-level network of 2n/2-input multiplexer modules as shown in Figure 1.41. The first level has 2n/2 multiplexers, and n/2 of the select inputs are used to select a group of 2n/2 from the 2n data inputs (one per multiplexer module). The second level uses the other n/2 select inputs to select one data input from the group already selected in the first level.
A high-level description of the network is as follows. The select input s is decomposed into two parts sL and sR so that
s = sL 2n/2 + sR
The vector sR is applied to the first level and the vector sL to the second. Consequently, the outputs of the first level are
j = 0, 1, … , 2n/2 -
1
and the output of the whole multiplexer is
Fig. 1.41 - Multiplexer tree.
The enable input E is applied to the multiplexer in the second level. A functional description of a two-level multiplexer tree is
where x is divided into n/2 subvectors of n/2 bits each, so that
(Remember that the three arguments of the MUX function are the data vector, the select vector, and the enable input.)
The network shown in Figure 1.42 implements a 16-input multiplexer because
and
where
The multiplexer-tree scheme can be generalized to the case in which there are r levels. If n=rk, the network uses (2n-1)/(2k-1) modules. This result is derived in a fashion similar to that for decoder trees.
Demultiplexer Networks
Since a demultiplexer is a decoder with a data input, a large demultiplexer can be implemented in the same ways as large decoders.
Encoder Networks
A 2n-input encoder can be implemented by a network of 2k-input encoders and some other modules. We assume in the following discussion that n = 2k.
Fig. 1.42 - 16-input multiplexor implementation.
1.8 Demultiplexers (Distributors)
A demultiplexer can be used to distribute
input information d
to
various outputs. It
represents an extension of the 1-out-of-n decoder. The addressed
output does not go to
"one", but assumes the value of input variable d.
Figure 1.43
illustrates the principle by means of switches, Fig. 1.44.
shows its implementation
using gates. If we make d
= const = 1, the
multiplexer operates as a 1-out-of-n
decoder. Commonly used demultiplexers are listed in Fig.
1.45
Fig. 1.43 - Basic mode of operation. Fig. 1.44 - Demultiplexer circuit.
Outputs |
TTL |
ECL |
CMOS |
16 |
74LS154 |
|
4514 |
8 |
74LS138 |
10162 |
74HC138 |
8 |
74ALS5381 |
|
40H.138 |
2 x 4 |
74LS139 |
10172 |
74HC139 |
2x4 |
74ALS5391 |
|
4555 |
1 Output polarity reversible
Fig. 1.45 - Integrated demultiplexers.
A 2n -output demultiplexer is a combinational system with n control (select) inputs s=(sn-1, . . . , s0), one data input x, a module-enable input E, and 2n data outputs y = ( , . . . , y0) (Figure 1.46.). It performs the inverse operation of the multiplexer: the input is routed to the output selected by the select variables. All other outputs are zero.
Fig. 1.46 - n-input demultiplexor.
A high-level description is
yi= |
x if i=s and E= 1 |
0 if i s and E=0 |
where
and
In the description of systems this module is denoted as
y = DMX(x,s,E)
For example, DMX(1, (1,0,1),1)=(0,0,1,0,0,0,0,0).
The switching expressions representing the outputs are
These expressions are similar to those of the decoder, the difference being the additional data input in the demultiplexer case. Consequently, a demultiplexer can be used as a decoder. The use of a decoder as a demultiplexer is also possible provided that the enable input of the decoder is used as the data input of the demultiplexer. Of course, in this last situation the resulting demultiplexer would not have an enable input. A vector demultiplexer can be defined in a manner similar to a vector multiplexer.
The basic use of a demultiplexer is to transmit the input to one out of several outputs under control of the select inputs.
