- •1 Combination Circuits
- •1.1 Circuitry ttl-elements with Shottky diodes
- •Levels of Integration
- •Typical Set of ttl iCs
- •Transistor-transistor logic (ttl)
- •1.2 Element with the open collector Open-collector outputs
- •Tristate outputs
- •1.3 Emitter-coupled logic (ecl)
- •Emitter-coupled multivibrator
- •Emitter-coupled Schmitt trigger
- •1.4 Decoder
- •Priority decoder
- •Binary Decoders
- •Decoder Networks
- •1.5 Coder units Encoder Networks
- •Binary Encoders
- •Priority Encoders
- •1.6 Multiplexers (Selectors)
- •1.7 Multiplexer Trees
- •Demultiplexer Networks
- •Encoder Networks
- •1.8 Demultiplexers (Distributors)
- •1.9 Applicanion of multiplexer
- •1.10 Code converters
- •1.11 Shifters
- •Shifter Networks
- •Barrel Shifter
- •1.12 Comparators
- •Window comparator
- •Digital comparators
- •2 Sequentional Circuits
- •2.1 Circuritry of flips
- •Sequential logic systems
- •Integrated flip-flops
- •Transparent flip-flops
- •Clocked rs flip-flop
- •Clocked d flip-flop
- •Flip-flops with intermediate storage
- •2.2 Flips types Single-edge-triggered flip-flops
- •2.3 Statik registers
- •2.4 Shift register Combinatorial shift register (barrel shifter)
- •Shift Registers
- •2.5 Counters
- •Asynchronous straight binary counter
- •Counters
- •Ripple Counters
- •Asynchronous bcd counter
- •2.6 Synchronous reversal counters
- •Synchronous straight binary counters
- •Synchronous bcd counter
- •Synchronous one-shot
- •Synchronous edge detector
- •Synchronous clock switch
- •2.7 Schmitt flip-flops Schmitt trigger
- •Inverting Schmitt trigger
- •Precision Schmitt trigger
- •3 Memory Devices
- •3.1 Circuitri of memori element Semiconductor memories
- •3.2 Mask-type lic of the rom
- •RaMs as shift registers
- •First-In-First-Out Memories (fifOs)
- •Fifo implementation using standard raMs
- •Error detection and correction
- •Parity bit
- •Hamming code
- •3.3 Rom with singl programming Read-only memories (roMs)
- •Mask-programmed roMs (mroMs)
- •Programmable roMs (proMs)
- •3.4 Memori element with electrical erase Electrically erasable proMs (eeproMs)
- •3.5 Static ram
- •Timing considerations
- •3.6 Dynamic raMs
- •Dynamic ram controllers
- •3.7 Devices programmed
- •Programmable logic array (pal)
Digital comparators
Comparators check two numbers, A
and
B,
against
one another, the relations of interest being A
= B, A > B and
A
< B. We
shall
first consider comparators
which determine whether two binary numbers are equal (identity
comparators).
The criterion for
this is that all corresponding bits of the two numbers
are identical. The comparator will produce at its output a logic 1 if
the numbers are equal,
otherwise a logic 0. In the simplest case, the two numbers consist
of only one bit each; to compare them, the equiv
operation (exclusive-nor
gate) may be used.
Two AT-bit numbers are compared bit by bit using an equiv
circuit for each
binary digit and the outputs are combined by an and
gate, as
shown in Fig. 1.68.
Fig. 1.68 - Identity comparator for two N-bit numbers.
IC-types:
2x8 inputs: SN74LS688 (TTL) from Texas-Instr.
2x9 inputs: Am29809 (TTL) from AMD.
2 x 10 inputs: SN74LS460 from MMI.
Comparators have a wider range of application if, in addition to indicating equality, they can also determine which of two numbers is the larger. Such circuits are known as magnitude comparators. To enable a comparison of the magnitude of two numbers, their code must be known, and for the following, we assume that both numbers are straight binary coded, i.e. that
.
The simplest case is again that of
comparing two single-bit numbers. The formulation
of the logic functions is based on the truth table of Fig.
1.69. From
these,
we can directly obtain the circuit in Fig.
1.70.
The following algorithm is used for
comparing numbers consisting of more than one bit: To begin with, the
most significant bit (MSB) of A is
compared
with the MSB of B.
If
they are different, these bits are sufficient to determine
the result. If they are equal, the next lower significant bit must
compared,
etc. If the identity variable of digit is denoted by g, as in Fig.
1.68,
the magnitude comparison of an W-digit number is given by the general
relation
Fig. 1.69 - Truth table of a 1-bit magnitude Fig. 1.70 - 1-bit magnitude
comparator. comparator.
.
1C types:
for 5-digit comparison: MC 10166 (ECL)
for 8-digit comparison: SN 74 LS682 . . . 689 (TTL).
The circuits can be cascaded serially or in parallel, Fig. 1.71 showing the serial method. When the 3 most significant bits are the same, the outputs of comparator C1 determine the result, as they are connected to the LSB inputs of comparator C2 (LSB = least significant bit).
When comparing many-bit numbers it is better to employ parallel cascading, as in Fig. 1.72, since the propagation delay time is shorter.
F
ig.
1.71 -
Serial
magnitude comparator.
Fig. 1.72 - Parallel magnitude comparator.
2 Sequentional Circuits
2.1 Circuritry of flips
Transistor T1 is on when a positive voltage is dropped across resistor R1 or resistor R2. If we also take into account the level inversion produced by the transistor, we can see that components R1 , R 2, T1 and RC form a nor gate. The same applies to the other half of the circuit. Inserting the appropriate circuit symbols, we obtain the circuit diagram shown in Fig. 2.1 with the associated truth table (Fig. 2.2).
Fig.
2.1 -
Flip-flop
comprising nor
gates.
Fig.
2.2 - Truth
table.
