- •Системы реального времени
- •Выдержка из документации на многофункциональный адаптер acl-8112 dg.
- •4. Registers Structure & Format
- •4.1 I/o Port Address
- •4.2 A/d Data Registers
- •4.3 A/d Channel Multiplexer Register
- •4.4 A/d Range Control Register
- •4.7 Software Trigger Register
- •4.5 A/d Operation Mode Control Register
- •4.6 Interrupt Status Register
- •4.8 Digital I/o register
- •4.9 D/a Output Register
- •4.10 Internal Timer/Counter Register
- •5 Operation Theorem
- •5.1 A/d Conversion
- •5.1.1 A/d Conversion Procedure
- •5.1.2 A/d Trigger Modes
- •5.1.3 A/d Data Transfer Modes
- •5.2 D/a Conversion
- •5.3 Digital Input and Output
- •5.4 Timer/Counter Operation
- •The 8254 Tinier I Counter Chip
- •Pacer Trigger Source
- •Выдержка из документации на адаптер аналогового вывода а626.
- •3. Programming
- •3.1. I/o Register
- •3.2. Data Register
4.5 A/d Operation Mode Control Register
The A/D operation includes the analog signal conversion and the data transformation. This register controls the internal trigger mode and data transformation method. It is initialized as software trigger and program polling transfer when your PC is reset or power on. The details of the A/D operation are illustrated in Chapter 5. There are four operation modes shown as following:
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
BASE+11 |
X |
X |
X |
X |
X |
S2 |
S1 |
S0 |
Attribute : write only
Data Format:
S2 |
S1 |
S0 |
Operation Mode Description |
0 |
0 |
0 |
Internal trigger is disable |
0 |
0 |
1 |
software trigger and program polling (default) |
0 |
1 |
0 |
timer pacer trigger and DMA transfer |
1 |
1- |
0 |
timer pacer trigger and interrupt transfer. |
Note:
When your system power on or reset, the A/D operation will be initialized as " software trigger and program polling" mode.
No matter which mode is selected, the external trigger is available if the JP4 is set to be external trigger.
As long as not the DMA mode is not used, the program polling is always possible. The synchronization of A/D conversion and data transfer should be concerned when use program polling.
The interrupt will be occurred after end of conversion if the "timer pacer trigger and interrupt transfer" mode is selected. If you want to use pacer trigger and interrupt transfer mode, please enable the IRQ level.
4.6 Interrupt Status Register
The Interrupt Status Register is used to clear the interrupt status for next new interrupt can be generated. If the DAS BOARD is in interrupt data transfer mode, a hardware status flag will be set after each A/D conversion. You have to clear the status flag by just writing any data to this register, let the DAS BOARD can generate next interrupt if a new A/D conversion is happen.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
BASE+8 |
X |
X |
X |
X |
X |
X |
X |
X |
Attribute : write only
Data Format:
4.7 Software Trigger Register
If you want to generate a trigger pulse to the DAS BOARD for A/D conversion, you just write any data to this register, and then the A/D converter will be triggered.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
BASE+12 |
X |
X |
X |
X |
X |
X |
X |
X |
Attribute : write only
Data Format:
