5 Operation Theorem

The operation theorem of the functions on DAS BOARD card is described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O and counter / timer. The operation theorem can help you to understand how to manipulate or to program the ACL-8112.

5.1 A/d Conversion

Before programming the DAS BOARD to perform the A/D conversion, you should understand the following issues:

• • A/D conversion procedure

• • A/D trigger mode

• • A/D data transfer mode

• • Signal Connection

5.1.1 A/d Conversion Procedure

The A/D conversion is starting by a trigger source, then the A/D converter will start to convert the signal to a digital value. The DAS BOARD provides three trigger modes, see section 5.1.2.

While A/D conversion, the DRDY bit in A/D data register is cleared to indicate the data is not ready. After conversion being completed, the DRDY bit will return to high (1) level. It means users can read the converted data from the A/D data registers. Please refer section 4.2 for the A/D data format.

The A/D data should be transferred into PC's memory for further using. The DAS BOARD provides three data transfer modes that allow users to optimize the DAS system. Refer to section 5.1.3 for data transfer modes.

5.1.2 A/d Trigger Modes

In the ACL-8112, A/D conversion can be triggered by the Internal or External trigger source. The jumper JP5 is used to select the internal or external trigger, please refer to section 2.8 for details. Whenever the external source is set, the internal sources are disable.

The two internal sources are the software trigger and the timer pacer trigger which is controlled by the A/D operation mode control register (BASE+11). Total three trigger sources are possible in the ACL-8112. The different trigger conditions are specified as follows:

Software trigger

The trigger source is software controllable in this mode. That is, the A/D conversion is starting when any value is written into the software trigger register (BASE+12). This trigger mode is suitable for low speed A/D conversion. Under this mode, the timing of the A/D conversion is fully controlled under software. However, it is difficult to control the fixed A/D conversion rate except another timer interrupt service routine is used to generate a fixed rate trigger.

Timer Pacer Trigger

An on-board timer / counter chip 8254 is used to provide a trigger source for A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded together to generate trigger pulse with precise period. Please refer to section 5.4 for 8254 architecture. This mode is ideal for high speed A/D conversion. It can be combined with the DMA or the interrupt data transfer. It's recommend to use this mode if your applications need a fixed and precise A/D sampling rate.

External Trigger

Through the pin-17 of CN3 (ExtTrig), the A/D conversion also can be performed when the a rising edge of external signal is occurred.

The conversion rate of this mode is more flexible than the previous two modes, because the users can handle the external signal by outside device. The external trigger can combine with the DMA transfer, interrupt data transfer, or even program polling data transfer. Generally, the interrupt data transfer is often used when external trigger mode is used.