- •Системы реального времени
- •Выдержка из документации на многофункциональный адаптер acl-8112 dg.
- •4. Registers Structure & Format
- •4.1 I/o Port Address
- •4.2 A/d Data Registers
- •4.3 A/d Channel Multiplexer Register
- •4.4 A/d Range Control Register
- •4.7 Software Trigger Register
- •4.5 A/d Operation Mode Control Register
- •4.6 Interrupt Status Register
- •4.8 Digital I/o register
- •4.9 D/a Output Register
- •4.10 Internal Timer/Counter Register
- •5 Operation Theorem
- •5.1 A/d Conversion
- •5.1.1 A/d Conversion Procedure
- •5.1.2 A/d Trigger Modes
- •5.1.3 A/d Data Transfer Modes
- •5.2 D/a Conversion
- •5.3 Digital Input and Output
- •5.4 Timer/Counter Operation
- •The 8254 Tinier I Counter Chip
- •Pacer Trigger Source
- •Выдержка из документации на адаптер аналогового вывода а626.
- •3. Programming
- •3.1. I/o Register
- •3.2. Data Register
Pacer Trigger Source
The counter 1 and counter 2 are cascaded together to generate the timer pacer trigger of A/D conversion. The frequency of the pacer trigger is software controllable. The maximum pacer signal rate is 2MHz/4=500K which excess the maximum A/D conversion rate of the ACL-8112. The minimum signal rate is 2MHz/65535/65535, which is a very slow frequency that user may never use it.
General Purpose Timer / Counter
The counter 0 is free for users' applications. The clock source, gate control signal and the output signal is send to the connector CN3. The general purpose timer / counter can be used as event counter, or used for measuring frequency, or others functions. See the 'Timer/Counter Applications' section for examples.
I/O Address
The 8254 in the DAS BOARD occupies 4 I/O address as shown below.
BASE + 0 |
LSB OR MSB OF COUNTER 0 |
BASE + 1 |
LSB OR MSB OF COUNTER 1 |
BASE + 2 |
LSB OR MSB OF COUNTER 2 |
BASE + 3 |
CONTROL BYTE |
The programming of 8254 is control by the registers BASE+0 to BASE+3. The functionality of each register is specified this section For more detailed information, please refer handbook of 8254 chip.
Control Byte
Before loading or reading any of these individual counters, the control byte (BASE+3) must be loaded first. The format of the control byte is:
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
SC1 |
SCO |
RL1 |
RLO |
M2 |
M1 |
MO |
BCD |
SC1 & SCO - Select Counter ( Bit7 & Bit 6)
SC1 |
SCO |
COUNTER |
0 |
0 |
Select Counter 0 |
0 |
1 |
Select Counter 1 |
1 |
0 |
Select Counter 2 |
1 |
1 |
ILLEGAL |
RL1 & RLO - Select Read/Load operation ( Bit 5 & Bit 4)
RL1 |
RLO |
OPERATION |
0 |
0 |
COUNTER LATCH FOR STABLE READ |
0 |
1 |
READ/LOAD LSB ONLY |
1 |
0 |
READ/LOAD MSB ONLY |
1 |
1 |
READ/LOAD LSB FIRST, THEN MSB |
M2, M1 & MO - Select Operatinq Mode ( Bit 3, Bit 2, & Bit 1)
M2 |
M1 |
MO |
MODE |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
X |
1 |
0 |
2 |
X |
1 |
1 |
3 |
1 |
0 |
0 |
4 |
1 |
0 |
1 |
5 |
BCD - Select Binary/BCD Countina ( Bit 0)
0 |
16-BITS BINARY COUNTER |
1 |
BINARY CODED DECIMAL (BCD) COUNTER (4 DIGITAL) |
Note The count of the binary counter is from 0 up to 65,535 and the count of the BCD counter is from 0 up to 9,999.
In 8254, six operating modes can be selected, they are:
Mode Definitions
Mode 0 Interrupt on Terminal Count
Mode 1 Programmable One-Shot.
Mode 2 Rate Generator.
Mode 3 Square Wave Rate Generator.
Mode 4 Software Triggered Strobe.
Mode 5 Hardware Triggered Strobe.
All detailed description of these six modes are written in Intel Microsystems Components Handbook Volume II Peripherals.
