- •1. Introduction
- •1.1 Chapter Outline
- •1.2 Server Board Use Disclaimer
- •2. Server Board Overview
- •2.1 Server Board Feature Set
- •2.2 Server Board Layout
- •2.2.1 Server Board Connector and Component Layout
- •2.2.2 Server Board Mechanical Drawings
- •2.2.3 Server Board ATX I/O Layout
- •3. Functional Architecture
- •3.1.1 System Bus Interface
- •3.1.2 Processor Support
- •3.1.2.1 Processor Population Rules
- •3.1.2.2 Common Enabling Kit (CEK) Design Support
- •3.1.3 Memory Subsystem
- •3.1.3.1 Memory RASUM Features
- •3.1.3.2 Supported Memory
- •3.1.3.3 DIMM Population Rules and Supported DIMM Configurations
- •3.1.3.4.1 Mirrored Mode Memory Configuration
- •3.1.3.4.2 Sparing Mode Memory Configuration
- •3.1.3.4.2.1 Single Branch Mode Sparing
- •3.1.3.4.2.2 Dual Branch Mode Sparing
- •3.1.4 Snoop Filter (5000X MCH only)
- •3.2.1 PCI Subsystem
- •3.2.1.3 PE0: One x4 PCI Express* Bus Segment
- •3.2.1.4 PE1: One x4 PCI Express* Bus Segment
- •3.2.1.5 PE2: One x4 PCI Express* Bus Segment
- •3.2.1.6 PE4, PE5: Two x4 PCI Express* Bus Segments
- •3.2.1.7 PE6, PE7: Two x4 PCI Express* Bus Segments
- •3.2.1.8 PCI Express* Riser Slot
- •3.2.2 Serial ATA Support
- •3.2.2.2 Intel® Embedded Server RAID Technology Option ROM
- •3.2.3 Parallel ATA (PATA) Support
- •3.2.4 USB 2.0 Support
- •3.3 Video Support
- •3.3.1 Video Modes
- •3.3.2 Video Memory Interface
- •3.3.3 Dual Video
- •3.4 SAS Controller
- •3.4.1 SAS RAID Support
- •3.4.2 SAS/SATA Connector Sharing
- •3.5 Network Interface Controller (NIC)
- •3.5.2 MAC Address Definition
- •3.6 Super I/O
- •3.6.1 Serial Ports
- •3.6.2 Floppy Disk Controller
- •3.6.3 Keyboard and Mouse Support
- •3.6.5 System Health Support
- •4. Platform Management
- •5. Connector/Header Locations and Pin-outs
- •5.1 Board Connector Information
- •5.2 Power Connectors
- •5.3 System Management Headers
- •5.3.2 LCP/AUX IPMB Header
- •5.3.3 IPMB Header
- •5.3.4 HSBP Header
- •5.3.5 SGPIO Header
- •5.3.7 HDD Activity LED Header
- •5.4 Front Panel Connector
- •5.5 I/O Connectors
- •5.5.1 VGA Connector
- •5.5.2 NIC Connectors
- •5.5.3 IDE Connector
- •5.5.5 SATA/SAS Connectors
- •5.5.6 Serial Port Connectors
- •5.5.7 Keyboard and Mouse Connector
- •5.5.8 USB Connector
- •5.6 Fan Headers
- •6. Jumper Blocks
- •6.1 CMOS Clear and Password Reset Usage Procedure
- •6.1.1 Clearing the CMOS
- •6.1.2 Clearing the Password
- •6.2 BMC Force Update Procedure
- •6.3 BIOS Select Jumper
- •7. Intel® Light-Guided Diagnostics
- •7.2 Fan Fault LEDs
- •7.3 System ID LED and System Status LED
- •7.3.1 System Status LED – BMC Initialization
- •7.4 DIMM Fault LEDs
- •7.5 Processor Fault LEDs
- •7.6 Post Code Diagnostic LEDs
- •8. Design and Environmental Specifications
- •8.3 Server Board Power Requirements
- •8.3.1 Processor Power Support
- •8.4.1 Grounding
- •8.4.2 Standby Outputs
- •8.4.3 Remote Sense
- •8.4.4 Voltage Regulation
- •8.4.5 Dynamic Loading
- •8.4.6 Capacitive Loading
- •8.4.7 Ripple/Noise
- •8.4.8 Timing Requirements
- •8.4.9 Residual Voltage Immunity in Standby Mode
- •9. Regulatory and Certification Information
- •9.1 Product Regulatory Compliance
- •9.1.1 Product Safety Compliance
- •9.1.2 Product EMC Compliance – Class A Compliance
- •9.1.3 Certifications/Registrations/Declarations
- •9.2 Product Regulatory Compliance Markings
- •9.3 Electromagnetic Compatibility Notices
- •9.3.1 FCC Verification Statement (USA)
- •9.3.3 Europe (CE Declaration of Conformity)
- •9.3.4 VCCI (Japan)
- •9.3.5 BSMI (Taiwan)
- •9.3.6 RRL (Korea)
- •9.4 Restriction of Hazardous Substances (RoHS) Compliance
- •Appendix A: Integration and Usage Tips
- •Appendix B: BMC Sensor Tables
- •Appendix C: POST Code Diagnostic LED Decoder
- •Appendix D: POST Code Errors
- •Appendix E: Supported Intel® Server Chassis
- •Glossary
- •Reference Documents
Intel® Server Boards S5000PSL and S5000XSL TPS |
Functional Architecture |
3.2.1PCI Subsystem
The primary I/O buses for the server board are PCI, PCI Express*, and PCI-X, with six independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification, Revision 2.3. The following table lists the characteristics of the PCI bus segments. Details about each bus segment follow the table.
Table 8. PCI Bus Segment Characteristics
PCI Bus Segment |
Voltage |
Width |
Speed |
Type |
PCI I/O Card Slots |
|
|
|
|
|
|
|
|
PCI32 |
3.3 |
V |
32-bit |
33 MHz |
PCI |
None. Used internally for video controller |
ESB2-E |
|
|
|
|
|
|
|
|
|
|
|
|
|
PXA |
3.3 |
V/5.0 V |
64-bit |
100 MHz |
PCI-X |
PCI-X Slot 1 |
ESB2-E |
|
|
|
|
|
|
|
|
|
|
|
|
|
PXA |
3.3 |
V/5.0 V |
64-bit |
133 MHz |
PCI-X |
PCI-X Slot 2 |
ESB2-E |
|
|
|
|
|
|
|
|
|
|
|
|
|
PE0 |
3.3 |
V |
x4 |
10 Gb/S |
PCI |
x4 throughput PCI Express* Slot 4 |
ESB2-E PCI |
|
|
|
|
Express* |
(Special keyed for ROMB card) |
Express* Port0 |
|
|
|
|
|
|
PE1 |
3.3 |
V |
x4 |
10 Gb/S |
PCI |
x4 throughput PCI Express* Slot 3 (SAS |
ESB2-E PCI |
|
|
|
|
Express* |
SKU); x8 throughput PCI Express* Slot 3 |
|
|
|
|
|
by combining PE2 and PE1 (SATA and |
|
Express* Port1 |
|
|
|
|
|
|
|
|
|
|
|
ROMB SKU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PE2 |
3.3 |
V |
x4 |
10 Gb/S |
PCI |
X4 throughput to on-board SAS (re-routed |
ESB2-E PCI |
|
|
|
|
Express* |
to Slot 3 in SATA SKU or ROMB SKU) |
Express* Port2 |
|
|
|
|
|
|
PE4, PE5 |
3.3 |
V |
x8 |
20 Gb/S |
PCI |
x8 throughput PCI Express* Slot 5 |
BNB PCI Express* |
|
|
|
|
Express* |
|
Ports 4, 5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PE6, PE7 |
3.3 |
V |
x8 |
20 Gb/S |
PCI |
x8 throughput PCI Express* Slot 6 |
BNB PCI Express* |
|
|
|
|
Express* |
|
Ports 6, 7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
3.2.1.1PCI32: 32-bit, 33-MHz PCI Subsystem
All 32-bit, 33-MHz PCI I/O is directed through the ESB2-E ICH6. The 32-bit, 33-MHz PCI segment created by the ESB2-E-ICH6 is known as the PCI32 segment. The PCI32 segment supports the following embedded devices:
2D Graphics Accelerator: ATI* ES1000 Video Controller
3.2.1.2PXA: 64-bit, 133-MHz PCI Subsystem
One 64-bit PCI-X bus segment is directed through the ESB2-E ICH6. This PCI-X segment, PXA, is routed to PCI-X Slots 1 and 2. With only one PCI-X adapter populated in Slot 2 and Slot 1 left empty, PCI-X Slot 2 supports a maximum speed of 133 MHz. With both Slot 1 and Slot 2 populated, Slot 2 supports a maximum speed of 100MHz. PCI-X Slot 1 supports a maximum speed of 100 MHz even when Slot 2 is not populated.
Revision 1.7 |
25 |
|
|
|
Intel order number: D41763-008 |
||
Functional Architecture |
Intel® Server Boards S5000PSL and S5000XSL TPS |
3.2.1.3PE0: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE0, is routed to PCI Express* Slot 4 that is special keyed to support ROMB card.
3.2.1.4PE1: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE1, is routed to PCI Express* Slot 3. This becomes a x8 PCI Express* bus segment by combining PE2 with PE1 for SATA server board or ROMB server board that do not have onboard SAS controller.
3.2.1.5PE2: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE2, is routed to PCI Express* Slot 3 for server boards that do not have on-board SAS controller (SATA server board or ROMB server board), or to the on-board SAS controller for server boards that do have on-board SAS controller (SAS server board).
3.2.1.6PE4, PE5: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express* segments, PE4 and PE5, are routed to PCI Express* Slot 5.
3.2.1.7PE6, PE7: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express* segments, PE6 and PE7, are routed to PCI Express* Slot 6.
3.2.1.8PCI Express* Riser Slot
PCI Express* Slot 6 supports third-party riser cards for both 1U and 2U system configurations. Two PCI Express* pins are designated as Riser Type pins with the definitions noted in the following table:
26 |
Revision 1.7 |
|
|
|
Intel order number: D41763-008 |
