- •1. Introduction
- •1.1 Chapter Outline
- •1.2 Server Board Use Disclaimer
- •2. Server Board Overview
- •2.1 Server Board Feature Set
- •2.2 Server Board Layout
- •2.2.1 Server Board Connector and Component Layout
- •2.2.2 Server Board Mechanical Drawings
- •2.2.3 Server Board ATX I/O Layout
- •3. Functional Architecture
- •3.1.1 System Bus Interface
- •3.1.2 Processor Support
- •3.1.2.1 Processor Population Rules
- •3.1.2.2 Common Enabling Kit (CEK) Design Support
- •3.1.3 Memory Subsystem
- •3.1.3.1 Memory RASUM Features
- •3.1.3.2 Supported Memory
- •3.1.3.3 DIMM Population Rules and Supported DIMM Configurations
- •3.1.3.4.1 Mirrored Mode Memory Configuration
- •3.1.3.4.2 Sparing Mode Memory Configuration
- •3.1.3.4.2.1 Single Branch Mode Sparing
- •3.1.3.4.2.2 Dual Branch Mode Sparing
- •3.1.4 Snoop Filter (5000X MCH only)
- •3.2.1 PCI Subsystem
- •3.2.1.3 PE0: One x4 PCI Express* Bus Segment
- •3.2.1.4 PE1: One x4 PCI Express* Bus Segment
- •3.2.1.5 PE2: One x4 PCI Express* Bus Segment
- •3.2.1.6 PE4, PE5: Two x4 PCI Express* Bus Segments
- •3.2.1.7 PE6, PE7: Two x4 PCI Express* Bus Segments
- •3.2.1.8 PCI Express* Riser Slot
- •3.2.2 Serial ATA Support
- •3.2.2.2 Intel® Embedded Server RAID Technology Option ROM
- •3.2.3 Parallel ATA (PATA) Support
- •3.2.4 USB 2.0 Support
- •3.3 Video Support
- •3.3.1 Video Modes
- •3.3.2 Video Memory Interface
- •3.3.3 Dual Video
- •3.4 SAS Controller
- •3.4.1 SAS RAID Support
- •3.4.2 SAS/SATA Connector Sharing
- •3.5 Network Interface Controller (NIC)
- •3.5.2 MAC Address Definition
- •3.6 Super I/O
- •3.6.1 Serial Ports
- •3.6.2 Floppy Disk Controller
- •3.6.3 Keyboard and Mouse Support
- •3.6.5 System Health Support
- •4. Platform Management
- •5. Connector/Header Locations and Pin-outs
- •5.1 Board Connector Information
- •5.2 Power Connectors
- •5.3 System Management Headers
- •5.3.2 LCP/AUX IPMB Header
- •5.3.3 IPMB Header
- •5.3.4 HSBP Header
- •5.3.5 SGPIO Header
- •5.3.7 HDD Activity LED Header
- •5.4 Front Panel Connector
- •5.5 I/O Connectors
- •5.5.1 VGA Connector
- •5.5.2 NIC Connectors
- •5.5.3 IDE Connector
- •5.5.5 SATA/SAS Connectors
- •5.5.6 Serial Port Connectors
- •5.5.7 Keyboard and Mouse Connector
- •5.5.8 USB Connector
- •5.6 Fan Headers
- •6. Jumper Blocks
- •6.1 CMOS Clear and Password Reset Usage Procedure
- •6.1.1 Clearing the CMOS
- •6.1.2 Clearing the Password
- •6.2 BMC Force Update Procedure
- •6.3 BIOS Select Jumper
- •7. Intel® Light-Guided Diagnostics
- •7.2 Fan Fault LEDs
- •7.3 System ID LED and System Status LED
- •7.3.1 System Status LED – BMC Initialization
- •7.4 DIMM Fault LEDs
- •7.5 Processor Fault LEDs
- •7.6 Post Code Diagnostic LEDs
- •8. Design and Environmental Specifications
- •8.3 Server Board Power Requirements
- •8.3.1 Processor Power Support
- •8.4.1 Grounding
- •8.4.2 Standby Outputs
- •8.4.3 Remote Sense
- •8.4.4 Voltage Regulation
- •8.4.5 Dynamic Loading
- •8.4.6 Capacitive Loading
- •8.4.7 Ripple/Noise
- •8.4.8 Timing Requirements
- •8.4.9 Residual Voltage Immunity in Standby Mode
- •9. Regulatory and Certification Information
- •9.1 Product Regulatory Compliance
- •9.1.1 Product Safety Compliance
- •9.1.2 Product EMC Compliance – Class A Compliance
- •9.1.3 Certifications/Registrations/Declarations
- •9.2 Product Regulatory Compliance Markings
- •9.3 Electromagnetic Compatibility Notices
- •9.3.1 FCC Verification Statement (USA)
- •9.3.3 Europe (CE Declaration of Conformity)
- •9.3.4 VCCI (Japan)
- •9.3.5 BSMI (Taiwan)
- •9.3.6 RRL (Korea)
- •9.4 Restriction of Hazardous Substances (RoHS) Compliance
- •Appendix A: Integration and Usage Tips
- •Appendix B: BMC Sensor Tables
- •Appendix C: POST Code Diagnostic LED Decoder
- •Appendix D: POST Code Errors
- •Appendix E: Supported Intel® Server Chassis
- •Glossary
- •Reference Documents
Connector/Header Locations and Pin-outs |
Intel® Server Boards S5000PSL and S5000XSL TPS |
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Table 35. External USB Connector Pin-out (JA6A1, JA6A2) |
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Signal Name |
Description |
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1 |
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USB_OC |
USB_PWR |
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2 |
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USB_PN |
DATAL0 (Differential data line paired with DATAH0) |
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3 |
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USB_PP |
DATAH0 (Differential data line paired with DATAL0) |
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4 |
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GND |
Ground |
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One 2x5 connector on the server board (J3J1) provides an option to support additional two USB ports. The pin-out of the connector is detailed in the following table:
Table 36. Internal USB Connector Pin-out (J3J1)
Pin |
Signal Name |
Description |
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1 |
USB2_VBUS5 |
USB power (port 5) |
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2 |
USB2_VBUS4 |
USB power (port 4) |
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3 |
USB_ESB_P5N_CONN |
USB port 5 negative signal |
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4 |
USB_ESB_P4N_CONN |
USB port 4 negative signal |
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5 |
USB_ESB_P5P_CONN |
USB port 5 positive signal |
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6 |
USB_ESB_P4P_CONN |
USB port 4 positive signal |
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7 |
Ground |
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8 |
Ground |
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9 |
Key |
No pin |
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10 |
TP_USB_ESB_NC |
Test point |
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5.6Fan Headers
The server board provides four SSI-compliant 4-pin and four SSI-compliant 6-pin fan headers to be used as CPU, and I/O cooling fans. 3-pin fans are supported on all fan headers. 6-pin fans are supported on headers J3H4, J3H3, J3H2, and J3H1. 4-pin fans are supported on headers J9J1, J5J1, J3H4, J3H3, J9B4, and J9B3. 4-pin fans are not supported on header J3H2, and J3H1, since these headers are tied to the CPU1 PWM. These fan headers should also not be used for CPU cooling fans. The pin configuration for each of the 4-pin and 6-pin fan headers is identical and is defined in the following tables.
Two 4-pin fan headers are designated as processor cooling fans:
-CPU1 fan (J9J1)
-CPU2 fan (J5J1)
Four 6-pin fan headers are designated as hot-swap system fans:
-Hot-swap system fan 1 (J3H4)
-Hot-swap system fan 2 (J3H3)
-Hot-swap system fan 3 (J3H2)
-Hot-swap system fan 4 (J3H1)
Two 4-pin fan headers are designated as rear system fans:
-System fan 5 (J9B4)
-System fan 6 (J9B3)
46 |
Revision 1.7 |
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Intel order number: D41763-008 |
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Intel® Server Boards S5000PSL and S5000XSL TPS |
Connector/Header Locations and Pin-outs |
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Table 37. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4) |
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Pin |
Signal Name |
Type |
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Description |
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1 |
Ground |
GND |
Ground is the power supply ground |
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2 |
12V |
Power |
Power supply 12 V |
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3 |
Fan Tach |
In |
FAN_TACH signal is connected to the BMC to monitor the fan speed |
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4 |
Fan PWM |
Out |
FAN_PWM signal to control fan speed |
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Table 38. SSI 6-pin Fan Header Pin-out (J3H1, J3H2, J3H3, J3H4) |
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Pin |
Signal Name |
Type |
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Description |
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1 |
Ground |
GND |
Ground is the power supply ground |
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2 |
12V |
Power |
Power supply 12 V |
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3 |
Fan Tach |
In |
FAN_TACH signal is connected to the BMC to monitor the fan speed |
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4 |
Fan PWM |
Out |
FAN_PWM signal to control fan speed |
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5 |
Fan Presence |
In |
Indicates the fan is present |
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6 |
Fan Fault LED |
Out |
Lights the fan fault LED |
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Note: Intel Corporation server boards support peripheral components and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.
Revision 1.7 |
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Intel order number: D41763-008 |
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