- •1. Introduction
- •1.1 Chapter Outline
- •1.2 Server Board Use Disclaimer
- •2. Server Board Overview
- •2.1 Server Board Feature Set
- •2.2 Server Board Layout
- •2.2.1 Server Board Connector and Component Layout
- •2.2.2 Server Board Mechanical Drawings
- •2.2.3 Server Board ATX I/O Layout
- •3. Functional Architecture
- •3.1.1 System Bus Interface
- •3.1.2 Processor Support
- •3.1.2.1 Processor Population Rules
- •3.1.2.2 Common Enabling Kit (CEK) Design Support
- •3.1.3 Memory Subsystem
- •3.1.3.1 Memory RASUM Features
- •3.1.3.2 Supported Memory
- •3.1.3.3 DIMM Population Rules and Supported DIMM Configurations
- •3.1.3.4.1 Mirrored Mode Memory Configuration
- •3.1.3.4.2 Sparing Mode Memory Configuration
- •3.1.3.4.2.1 Single Branch Mode Sparing
- •3.1.3.4.2.2 Dual Branch Mode Sparing
- •3.1.4 Snoop Filter (5000X MCH only)
- •3.2.1 PCI Subsystem
- •3.2.1.3 PE0: One x4 PCI Express* Bus Segment
- •3.2.1.4 PE1: One x4 PCI Express* Bus Segment
- •3.2.1.5 PE2: One x4 PCI Express* Bus Segment
- •3.2.1.6 PE4, PE5: Two x4 PCI Express* Bus Segments
- •3.2.1.7 PE6, PE7: Two x4 PCI Express* Bus Segments
- •3.2.1.8 PCI Express* Riser Slot
- •3.2.2 Serial ATA Support
- •3.2.2.2 Intel® Embedded Server RAID Technology Option ROM
- •3.2.3 Parallel ATA (PATA) Support
- •3.2.4 USB 2.0 Support
- •3.3 Video Support
- •3.3.1 Video Modes
- •3.3.2 Video Memory Interface
- •3.3.3 Dual Video
- •3.4 SAS Controller
- •3.4.1 SAS RAID Support
- •3.4.2 SAS/SATA Connector Sharing
- •3.5 Network Interface Controller (NIC)
- •3.5.2 MAC Address Definition
- •3.6 Super I/O
- •3.6.1 Serial Ports
- •3.6.2 Floppy Disk Controller
- •3.6.3 Keyboard and Mouse Support
- •3.6.5 System Health Support
- •4. Platform Management
- •5. Connector/Header Locations and Pin-outs
- •5.1 Board Connector Information
- •5.2 Power Connectors
- •5.3 System Management Headers
- •5.3.2 LCP/AUX IPMB Header
- •5.3.3 IPMB Header
- •5.3.4 HSBP Header
- •5.3.5 SGPIO Header
- •5.3.7 HDD Activity LED Header
- •5.4 Front Panel Connector
- •5.5 I/O Connectors
- •5.5.1 VGA Connector
- •5.5.2 NIC Connectors
- •5.5.3 IDE Connector
- •5.5.5 SATA/SAS Connectors
- •5.5.6 Serial Port Connectors
- •5.5.7 Keyboard and Mouse Connector
- •5.5.8 USB Connector
- •5.6 Fan Headers
- •6. Jumper Blocks
- •6.1 CMOS Clear and Password Reset Usage Procedure
- •6.1.1 Clearing the CMOS
- •6.1.2 Clearing the Password
- •6.2 BMC Force Update Procedure
- •6.3 BIOS Select Jumper
- •7. Intel® Light-Guided Diagnostics
- •7.2 Fan Fault LEDs
- •7.3 System ID LED and System Status LED
- •7.3.1 System Status LED – BMC Initialization
- •7.4 DIMM Fault LEDs
- •7.5 Processor Fault LEDs
- •7.6 Post Code Diagnostic LEDs
- •8. Design and Environmental Specifications
- •8.3 Server Board Power Requirements
- •8.3.1 Processor Power Support
- •8.4.1 Grounding
- •8.4.2 Standby Outputs
- •8.4.3 Remote Sense
- •8.4.4 Voltage Regulation
- •8.4.5 Dynamic Loading
- •8.4.6 Capacitive Loading
- •8.4.7 Ripple/Noise
- •8.4.8 Timing Requirements
- •8.4.9 Residual Voltage Immunity in Standby Mode
- •9. Regulatory and Certification Information
- •9.1 Product Regulatory Compliance
- •9.1.1 Product Safety Compliance
- •9.1.2 Product EMC Compliance – Class A Compliance
- •9.1.3 Certifications/Registrations/Declarations
- •9.2 Product Regulatory Compliance Markings
- •9.3 Electromagnetic Compatibility Notices
- •9.3.1 FCC Verification Statement (USA)
- •9.3.3 Europe (CE Declaration of Conformity)
- •9.3.4 VCCI (Japan)
- •9.3.5 BSMI (Taiwan)
- •9.3.6 RRL (Korea)
- •9.4 Restriction of Hazardous Substances (RoHS) Compliance
- •Appendix A: Integration and Usage Tips
- •Appendix B: BMC Sensor Tables
- •Appendix C: POST Code Diagnostic LED Decoder
- •Appendix D: POST Code Errors
- •Appendix E: Supported Intel® Server Chassis
- •Glossary
- •Reference Documents
Functional Architecture |
Intel® Server Boards S5000PSL and S5000XSL TPS |
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Table 6. Maximum Eight-DIMM System Memory Configuration – x2 Quad Rank |
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DRAM Technology |
Maximum Capacity |
Maximum Capacity |
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x2 Quad Rank |
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Non-mirrored Mode |
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32 GB |
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1024 Mb |
16 GB |
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32 GB |
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2048 Mb |
16 GB |
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Note: Only fully buffered DDR2 DIMMs (FBDIMMs) are supported on this server board. For a list of supported memory for this server board, see http://www.intel.com/support/motherboards/server/s5000psl/sb/CS-022924.htm.
3.1.3.3DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller, which is determined by the number of DIMMs installed. DIMMs must be populated in pairs. DIMM pairs are populated in the following DIMM slot order: A1 and B1, C1 and D1, A2 and B2, C2 and D2. DIMMs within a given pair must be identical with respect to size, speed, and organization. However, DIMM capacities can be different between different DIMM pairs.
For example, a valid mixed DIMM configuration may have 512-MB DIMMs installed in DIMM slots A1 and B1, and 1-GB DIMMs installed in DIMM slots C1 and D1.
Intel supported DIMM configurations for this server board are shown in the following table:
Supported and Validated configuration : Slot is populated
Supported but not validated configuration : Slot is populated
Slot is not populated
Mirroring: Y = Yes. Indicates that configuration supports Memory Mirroring. Sparing: Y(x) = Yes. Indicates that configuration supports Memory Sparing.
Where x = 0 : Sparing supported on Branch 0 only 1 : Sparing supported on Branch 1 only
0, 1 : Sparing supported on both branches
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Revision 1.7 |
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Intel order number: D41763-008 |
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Intel® Server Boards S5000PSL and S5000XSL TPS |
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Functional Architecture |
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Table 7. Supported DIMM Configurations |
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Branch 0 |
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Branch 1 |
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Mirroring |
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Sparing |
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Channel A |
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Channel B |
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Channel C |
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Channel D |
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Possible |
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DIMM_A |
DIMM_A |
DIMM_B |
DIMM B2 |
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DIMM C1 |
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DIMM C2 |
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DIMM D1 |
DIMM D2 |
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1 |
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1 |
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Y (0) |
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Y |
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Y (0) |
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Y |
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Y (0, 1) |
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Notes:
Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1.
The supported memory configurations must meet population rules defined above.
For best performance, the number of DIMMs installed should be balanced across both memory branches. For example: a four-DIMM configuration will perform better than a two-DIMM configuration and should be installed in DIMM slots A1, B1, C1, and D1. An eight-DIMM configuration will perform better then a six-DIMM configuration.
Although mixed DIMM capacities between channels are supported, Intel does not validate DIMMs in mixed DIMM configurations.
3.1.3.3.1Minimum Non-Mirrored Mode Configuration
The server board is capable of supporting a minimum of one DIMM installed. However, for system performance reasons, Intel’s recommendation is that at least two DIMMs be installed.
The following diagram shows the recommended minimum DIMM memory configuration. Populated DIMM slots are shown in gray.
MCH
Branch 0
Channel B |
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Channel C |
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Channel A |
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Channel D |
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A1 |
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DIMM |
A2 |
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DIMM B1 |
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DIMM |
B2 |
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DIMM C1 |
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DIMM C2 |
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DIMM D1 |
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DIMM |
D2 |
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DIMM |
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Branch 1 |
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TP02300 |
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Figure 13. Minimum Two DIMM Memory Configuration |
Revision 1.7 |
21 |
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Intel order number: D41763-008 |
Functional Architecture |
Intel® Server Boards S5000PSL and S5000XSL TPS |
Note: The server board supports single DIMM mode operation. Intel will only validate and support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1.
3.1.3.4Non-mirrored Mode Memory Upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the same slot position on both channels. DIMMs pairs must be identical with respect to size, speed, and organization. DIMMs that cover adjacent slot positions do not need to be identical.
When adding two DIMMs to the configuration shown in Figure 13 (above), the DIMMs should be populated in DIMM sockets C1 and D1 as shown in the following figure. Populated DIMM sockets are shown in gray.
MCH
Branch 0
Channel B |
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Channel C |
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Channel A |
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Channel D |
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A1 |
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DIMM |
A2 |
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DIMM B1 |
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DIMM |
B2 |
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DIMM C1 |
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DIMM C2 |
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DIMM D1 |
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DIMM |
D2 |
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DIMM |
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Branch 1
TP02301
Figure 14. Recommended Four DIMM Configuration
Functionally, DIMM sockets A2 and B2 could also have been populated instead of DIMM sockets C1 and D1. However, your system will not achieve equivalent performance. Figure 13 on the previous page, shows the supported DIMM configuration that is recommended because it allows both branches to operate independently and simultaneously. FBD bandwidth is doubled when both branches operate in parallel.
3.1.3.4.1Mirrored Mode Memory Configuration
When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch 1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support memory mirroring is four DIMMs, populated as shown in Figure 14, above. All four DIMMs must be identical with respect to size, speed, and organization.
To upgrade a four-DIMM mirrored memory configuration, four additional DIMMs must be added to the system. All four DIMMs in the second set must be identical to the first with the exception of speed. The MCH will adjust to the lowest speed DIMM.
22 |
Revision 1.7 |
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Intel order number: D41763-008 |
