Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
ON-CHIP EMULATION (OnCE) PINS
2.2.7.2Serial Control One (SC1)
The SSI uses this bidirectional pin to control flag or frame synchronization. This pin’s function is determined by whether the SCLK is in synchronous or asynchronous mode.In asynchronous mode, this pin is frame sync I/O. For synchronous mode with continuous clock, this pin is serial flag SC1 and operates like the SC0. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC1 can be programmed as a general-purpose I/O pin (PC4) when the SSI SC1 function is not being used, and it is configured as a GPIO input pin during hardware reset.
2.2.7.3Serial Control Two (SC2)
The SSI uses this bidirectional pin to control frame synchronization only. As with SC0 and SC1, its function is defined by the SSI operating mode. SC2 can be programmed as a general-purpose I/O pin (PC5) when the SSI SC2 function is not being used, and it is configured as a GPIO input pin during hardware reset.
2.2.7.4SSI Serial Clock (SCK)
This bidirectional pin provides the serial bit rate clock for the SSI when only one clock is being used. SCK can be programmed as a general-purpose I/O pin (PC6) when it is not needed as an SSI pin, and it is configured as a GPIO input pin during hardware reset.
2.2.7.5SSI Receive Data (SRD)
This input pin receives serial data into the SSI receive shift register. SRD can be programmed as a general-purpose I/O pin (PC7) when it is not needed as an SSI pin, and it is configured as a GPIO input pin during hardware reset.
2.2.7.6SSI Transmit Data (STD)
This output pin transmits serial data from the SSI transmit shift register. STD can be programmed as a general-purpose I/O pin (PC8) when it is not needed as an SSI pin, and it is configured as a GPIO input pin during hardware reset.
2.3ON-CHIP EMULATION (OnCE) PINS
The following paragraphs describe the OnCE pins associated with the OnCE controller and its serial interface.
2.3.1Debug Serial Input/Chip Status 0 (DSI/OS0)
Serial data or commands are provided to the OnCE controller through the DSI/OS0 pin when it is an input. The data received on the DSI pin will be recognized only when the DSP56K has entered the debug mode of operation. Data is latched on the falling edge of
MOTOROLA DSP56002 PIN DESCRIPTIONS 2 - 11
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
ON-CHIP EMULATION (OnCE) PINS
the DSCK serial clock. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSI/OS0 pin is an output, it works in conjunction with the OS1 pin to provide chip status information (see Section 10 ON CHIP EMULATION (OnCE) in the DSP56000 Family Manual). The DSI/OS0 pin is an output when the processor is not in debug mode. When switching from output to input, the pin is three-stated. During hardware reset, this pin is defined as an output and it is driven low.
Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin.
2.3.2Debug Serial Clock/Chip Status 1 (DSCK/OS1)
The DSCK/OS1 pin supplies the serial clock to the OnCE when it is an input. The serial clock provides pulses required to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency.
The pin is three-stated when it is changing from input to output. When it is an output, it works with the OS0 pin to provide information about the chip status (see SECTION 10 ON CHIP EMULATION (OnCE) in the DSP56000 Family Manual). It is an output when the chip is not in debug mode. During hardware reset, this pin is defined as an output and is driven low.
Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin.
2.3.3Debug Serial Output (DSO)
The DSP reads serial data from the OnCE through the DSO output pin, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port most significant bit (MSB) first. Data is clocked out of the OnCE serial port on the rising edge of DSCK.
The DSO pin also provides acknowledge pulses to the external command controller.
When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After receiving a read command, the DSO pin will be pulsed low to indicate that the requested data is available and the
OnCE serial port is ready to receive clocks in order to deliver the data. After receiving a write command, the DSO pin will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.
During hardware reset and when the processor is idle, the DSO pin is held high.
2 - 12 DSP56002 PIN DESCRIPTIONS MOTOROLA
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