Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

tine. The most significant bit (HREQ) of the ISR may be tested by the host processor to determine if the DSP is the interrupting device and the two least significant bits (RXDF and TXDE) may be tested to determine the interrupt source (see Figure 5-17). The host processor interrupt service routine must read or write the appropriate HI register to clear the interrupt. HREQ is deasserted when1) the enabled request is cleared or masked, 2) DMA HACK is asserted, or 3) the DSP is reset.

5.3.5.3Polling

In the polling mode of operation, the HREQ pin is not connected to the host processor and HACK must be deasserted to insure DMA data or IVR data is not being output on H0-H7 when other registers are being polled.

The host processor first performs a data read transfer to read the ISR (see Figure 5-17) to determine, whether:

1.RXDF=1, signifying the receive data register is full and therefore a data read should be performed

2.TXDE=1, signifying the transmit data register is empty so that a data write can be performed

3.TRDY=1, signifying the transmit data register is empty and that the receive data register on the DSP CPU side is also empty so that the data written by the host processor will be transferred directly to the DSP side

4.HF2 • HF3 ≠ 0, signifying an application-specific state within the DSP CPU has been reached, which requires action on the part of the host processor

5.DMA=1, signifying the HI is currently being used for DMA transfers. If DMA transfers are possible in the system, deactivate HACK prior to reading the ISR so both DMA data and the contents of ISR are not simultaneously output on

H0H7

6.If HREQ=1, the HREQ pin has been asserted, and one of the previous five conditions exists

Generally, after the appropriate data transfer has been made, the corresponding status bit will toggle.

If the host processor has issued a command to the DSP by writing the CVR and setting the HC bit, it can read the HC bit in the CVR to determine when the command has been accepted by the interrupt controller in the DSP’s central processing module. When the command has been accepted for execution, the interrupt controller will reset the HC bit.

5 - 36 PORT B MOTOROLA

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

HREQ ASSERTED

HREQ

Figure 5-17 HI Interrupt Structure

5.3.5.4Servicing Non-DMA Interrupts

When HM0=HM1=0 (non-DMA) and HREQ is connected to the host processor interrupt input, the HI can request service from the host processor by asserting HREQ. In the nonDMA mode, HREQ will be asserted when TXDE=1 and/or RXDF=1 and the corresponding mask bit (TREQ or RREQ, respectively) is set. This is depicted in Figure 5-17.

Generally, servicing the interrupt starts with reading the ISR, as described in the previous section on polling, to determine which DSP has generated the interrupt and why. When multiple DSPs occur in a system, the HREQ bit in the ISR will normally be read first to determine the interrupting device. The host processor interrupt service routine must read or write the appropriate HI register to clear the interrupt. HREQ is deasserted when the enabled request is cleared or masked.

In the case where the host processor is a member of the MC680XX Family, servicing the interrupt will start by asserting HREQ to interrupt the processor (see Figure 5-17). The host processor then acknowledges the interrupt by asserting HACK. While HREQ and HACK are simultaneously asserted, the contents of the IVR are placed on the host data bus. This vector will tell the host processor which routine to use to service the HREQ interrupt.

The HREQ pin is an open-drain output pin so that it can be wire-ORed with the HREQ pins from other DSP56002 processors in the system. When the DSP56002 generates an interrupt request, the host processor can poll the HREQ bit in each of the ISRs to determine which device generated the interrupt.

MOTOROLA PORT B 5 - 37

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