Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

5.3.5.5Servicing DMA Interrupts

When HM0≠0 and/or HM1≠0, HREQ will be asserted to request a DMA transfer. Generally the HREQ pin will be connected to the REQ input of a DMA controller. The HA0-2, HEN, and HR/W pins are not used during DMA transfers; DMA transfers only use the HREQ and HACK pins after the DMA channel has been initialized. HACK is used to strobe the data transfer as shown in Figure 5-18 where an MC68440 is used as the DMA controller. DMA transfers to and from the HI are considered in more detail in Section 5.3.6 HI Application Examples.

5.3.6HI Application Examples

The following paragraphs describe examples of initializing the HI, transferring data with the HI, bootstrapping via the HI, and performing DMA transfers through the HI.

5.3.6.1HI Initialization

Initializing the HI takes two steps (see Figure 5-19). The first step is to initialize the DSP

1 DMA CYCLE = 8T = 4 DMA CLOCK CYCLES MAX. MC68440 CLOCK = 10 MHz = > T = 50 ns

Figure 5-18 DMA Transfer Logic and Timing

5 - 38 PORT B MOTOROLA

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

STEP 1

THE DSP CPU INITIALIZES THE DSP SIDE OF

THE HI BY WRITING:

1)HCR AT X:$FFE8 AND

2)PBC AT X:$FFE0

STEP 2

THE HOST PROCESOR INITIALIZES THE

HOST SIDE OF THE HI BY WRITING:

1)ICR AT $0 AND/OR

2)CVR AT $1 AND/OR

3)IVR AT $3

Figure 5-19 HI Initialization Flowchart

side of the HI, which requires that the options for interrupts and flags be selected and then the HI be selected (see Figure 5-20). The second step is for the host processor to clear the HC bit by writing the CVR, select the data transfer method - polling, interrupts, or DMA (see Figure 5-21 (d) and Figure 5-23), and write the IVR in the case of a MC680XX Family host processor. Figure 5-19 through Figure 5-22 provide a general description of how to initialize the HI. Later paragraphs in this section provide more detailed descriptions for specific examples.These subsections include some code fragments illustrating how to initialize and transfer data using the HI.

5.3.6.2Polling/Interrupt Controlled Data Transfer

Handshake flags are provided for polled or interrupt-driven data transfers. Because the DSP interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed I/O (non-DMA) instruction rate without testing the handshake flags for each transfer. If the full handshake is not needed, the host processor can treat the DSP as fast memory, and data can be transferred between the host and DSP at the fastest host processor rate. DMA hardware may be used with the external host request and host acknowledge pins to transfer data at the maximum DSP interrupt rate.

The basic data transfer process from the host processor’s view (see Figure 5-15) is for the host to:

1.Assert HREQ when the HI is ready to transfer data

2.Assert HACK If the interface is using HACK

3.Assert HR/W to select whether this operation will read or write a register

4.Assert the HI address (HA2, HA1, and HA0) to select the register to be read or written

MOTOROLA PORT B 5 - 39

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

5.Assert HEN to enable the HI

6.When HEN is deasserted, the data can be latched or read as appropriate if the timing requirements have been observed

7.HREQ will be deasserted if the operation is complete

STEP 1 OF HOST PORT CONFIGURATION

1.ENABLE/DISABLE

HOST RECEIVE DATA FULL INTERRUPT ENABLE INTERRUPT: BIT 0 = 1 DISABLE INTERRUPT: BIT 0 = 0

2, ENABLE/DISABLE

HOST TRANSMIT DATA EMPTY INTERRUPT ENABLE INTERRUPT: BIT 1 = 1

DISABLE INTERRUPT: BIT 1 = 0

3.ENABLE/DISABLE

HOST COMMAND PENDING INTERRUPT ENABLE INTERRUPT: BIT 2 = 1 DISABLE INTERRUPT: BIT 2 = 0

4.SET/CLEAR

HOST FLAG 2 (OPTIONAL) ENABLE FLAG: BIT 3 = 1 DISABLE FLAG: BIT 3 = 0

5. SET/CLEAR

HOST FLAG 3 (OPTIONAL) ENABLE FLAG: BIT 4 = 1 DISABLE FLAG: BIT 4 = 0

* Reserved; write as zero.

NOTE: The host flags are general-purpose semaphores. They are not required for host port operation but may be used in some applications.

Figure 5-20 HI Initialization–DSP Side

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