Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

interrupt vector (IV) location divided by two - i.e. if HV=$12, IV=$24).

2.The HC is then set.

3.The HCP bit in the HSR is set when HC is set.

4.If the HCIE bit in the HCR has been set by the DSP, the HC exception processing will start. The HV is multiplied by 2 and the result is used by the DSP as the interrupt vector.

5.When the HC exception is acknowledged, the HC bit (and therefore the HCP bit) is cleared by the HC logic. HC can be read by the host processor as a status bit to determine when the command is accepted. Similarly, the HCP bit can be read by the DSP CPU to determine if an HC is pending.

To guarantee a stable interrupt vector, write HV only when HC is clear. The HC bit and

HV can be written simultaneously. The host processor can clear the HC bit to cancel a host command at any time before the DSP exception is accepted. Although the HV can be programmed to any exception vector, it is not recommended that HV=0 (RESET) be used because it does not reset the DSP hardware. DMA must be disabled to use the host exception.

5.3.6.2.3Host to DSP - Bootstrap Loading Using the HI

The circuit shown in Figure 5-29 will cause the DSP to boot through the HI on power up. During the bootstrap program, the DSP looks at the MODC, MODB, and MODA bits. If

Figure 5-25 Receive Data from Host–Main Program

;************************************

; Receive from Host Interrupt Routine ;************************************

RCV MOVEP X:HRX,X:(R0)+ ;Receive data.

RTI

END

Figure 5-26 Receive Data from Host Interrupt Routine

MOTOROLA PORT B 5 - 49

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SETTING HF0 TERMINATES BOOTSTRAP LOADING AND STARTS

EXECUTION AT LOCATION P:$0000.

• Because the DSP56002 is so fast, host handshaking is generally not required.

Figure 5-29 Bootstrap Using the HI

5 - 50 PORT B MOTOROLA

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

the bits are set at 101 respectively, the DSP will load from the HI. Data is written by the host processor in a pattern of four bytes, with the high byte being a dummy and the low byte being the low byte of the DSP word (see Figure 5-29 and Figure 5-30). Figure 5-30 shows how an 8-,16-, 24-, or 32-bit word in the host processor maps into the HI registers. The HI register at address $4 is not used and will read as zero. It is not necessary to use address $4, but since many host processors are 16or 32-bit processors, address $4 will often be used as part of the 16or 32-bit word. The low order byte (at $7) should always be written last since writing to it causes the HI to initiate the transfer of the word to the HRX. Data is then transferred from the HRX to the DSP program memory. If the host processor needs to terminate the bootstrap loading before 512 words have been down loaded, it can set the HF0 bit in the ICR. The DSP will then terminate the down load and start executing at location P:$0000. Since the DSP56002 is typically faster than the host processor, hand shaking during the data transfer is normally not required.

The actual code used in the bootstrap program is given in APPENDIX A. The portion of the code that loads from the HI is shown in Figure 5-31. The BSET instruction configures

24-BIT TRANSFER

32-BIT TRANSFER, LS 24 BITS ARE SIGNIFICANT

NOTE: Access low byte last

Figure 5-30 Transmit/Receive Byte Registers

MOTOROLA PORT B 5 - 51

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