Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

2. OPTION 4: LOAD HOST INTERRUPT VECTOR IF USING THE INTERRUPT MODE AND THE HOST PROCESSOR REQUIRES AN INTERRUPT VECTOR.

*Reserved; write as zero.

**See Figure 10 - 23.

Figure 5-21 (c) HI Initialization–Host Side, Interrupt Mode

described. Figure 5-24 illustrates the process of that data transfer. The steps in Figure 5- 24 can be summarized as follows:

1.When the TXDE bit in the ISR is set, it indicates that the HI is ready to receive a data byte from the host processor because the transmit byte registers (TXH, TXM, TXL) are empty.

2.The host processor can poll as shown in this step.

3.Alternatively, the host processor can use interrupts to determine the status of this bit. Setting the TREQ bit in the ICR causes the HREQ pin to interrupt the host processor when TXDE is set.

4.Once the TXDE bit is set, the host can write data to the HI. It does this by writing three bytes to TXH, TXM, and TXL, respectively, or two bytes to TXM and TXL, respectively, or one byte to TXL.

5.Writing data to TXL clears TXDE in the ISR.

6.From the DSP’s viewpoint, the HRDF bit (when set) in the HSR indicates that data is waiting in the HI for the DSP.

5 - 42 PORT B MOTOROLA

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Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

7.When the DSP reads the HRX, the HRDF bit is automatically cleared and TXDE in the ISR is set.

8.When TXDE=0 and HRDF=0, data is automatically transferred from TBR to HRX which sets HRDF.

9.The DSP can poll HRDF to see when data has arrived, or it can use interrupts.

10.If HRIE (in the HCR) and HRDF are set, exception processing is started using interrupt vector P:$0020.

The code shown in Figure 5-25 is an excerpt from the Host I/O Port Technical Bulletin (inhouse document). The MAIN PROGRAM initializes the HI and then hangs in a wait loop while it allows interrupts to transfer data from the host processor to the DSP. The first three MOVEP instructions enable the HI and configure the interrupts. The following MOVE enables the interrupts (this should always be done after the interrupt programs and hardware are completely initialized) and prepares the DSP CPU to look for the host flag, HF0=1. The JCLR instruction is a polling loop that looks for HF0=1, which indicates that the host processor is ready. When the host processor is ready to transfer data to the DSP, the DSP enables HRIE in the HCR, which allows the interrupt routine to receive data from the host processor. The jump-to-self instruction that follows is for test purposes only, it can be replaced by any other code in normal operation.

STEP 2 OF HOST PORT CONFIGURATION

2. OPTION 5: SELECT DMA MODE FOR

INITIALIZE DSP

INITIALIZE HI**

BIT 7 = 1

*Reserved; write as zero.

**See Figure 5-23.

Figure 5-21 (d) HI Initialization–Host Side, DMA Mode

MOTOROLA PORT B 5 - 43

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