Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
HOST INTERFACE (HI)
5.3.6.4Example Circuits
Figure 5-41, Figure 5-42, and Figure 5-43 illustrate the simplicity of the HI. The MC68HC11 in Figure 5-42 has a multiplexed address and data bus which requires that the address be latched. Although the HACK is not used in this circuit, it is pulled up. All unused input pins should be terminated to prevent erroneous signals. When determining whether a pin is an input, keep in mind that it may change during reset or while changing Port B between general purpose I/O and HI functions.
The MC68000 (see Figure 5-42) can use a MOVEP instruction with word and long-word data size to transfer multiple bytes. If an MC68020 or MC68030 is used, dynamic bus sizing can be used to transfer multiple bytes with any instruction.
Figure 5-43 is a high level block diagram of a system using a single host to control multiple
DSPs. In addition, the DSPs use the SSI to network together the DSPs and multiple codecs. This system, as shown with four DSPs, can process 80 million instructions per
MC68HC11
IRQ
A8 - A15
E
R/W
AS
A0/D0 - A7/D7
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+5 V |
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+5 V |
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ADDRESS |
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DECODE |
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A3 |
- A7 |
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LE |
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A0 - A2 |
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ADDRESS |
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LATCH |
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DSP56002
HACK
(HOST ACKNOWLEDGE)
HREQ
(HOST REQUEST)
HEN
(HOST ENABLE)
HR/W
(HOST READ/WRITE)
HA0 - HA2
(HOST ADDRESS)
H0 - H7 (HOST DATA)
Use LDA and STA for 8-Bit Transfers.
Use LDD and STD for 16-Bit Transfers.
Figure 5-41 MC68HC11 to DSP56002 Host Interface
MOTOROLA PORT B 5 - 63
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
HOST INTERFACE (HI)
MC68000
IPL0 - IPL2
A4 - A23
FC0 - FC2
LDS
AS
DTACK
BERR
R/W
A1 - A3
D0 - D7
+5 V |
INTERRUPT |
ENCODER |
ADDRESS |
DECODE |
INTERRUPT |
VECTOR |
DECODE |
DTACK |
TIMING |
GENERATOR |
DSP56002
HREQ
HEN
HACK
HR/W
HA0 - HA2
H0 - H7
MC68000 — USE MOVEP for multiple byte transfers.
MC68020 or MC68030 — Any Memory references will work due to dynamic bus sizing.
Figure 5-42 MC68000 to DSP56002 Host Interface
second at 40 MHz and can be easily expanded if more processing power is needed.
5 - 64 PORT B MOTOROLA
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
HOST INTERFACE (HI)
REQ |
RD/WR |
ADDRESS BUS |
DATA BUS |
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HOST |
SSI |
SELECT |
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DSP56002 |
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HOST |
SSI |
SELECT |
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DATA |
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DSP56002 |
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ADDRESS |
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HOST |
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RD/WR |
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REQ |
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HOST |
SSI |
SELECT |
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DSP56002 |
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HOST |
SSI |
SELECT |
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DSP56002 |
FLAG 0 |
FLAG 1 |
CLOCK |
FRAME SYNC |
SERIAL DATA |
RX |
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ANALOG |
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INPUT |
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CODEC |
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ANALOG |
TX |
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OUTPUT |
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RX |
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TX |
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RX |
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ANALOG |
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INPUT |
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CODEC |
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ANALOG |
TX |
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OUTPUT |
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RX |
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Figure 5-43 Multi-DSP Network Example
MOTOROLA PORT B 5 - 65
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
HOST INTERFACE (HI)
5.3.6.5Host Port Usage Considerations – Host Side
Synchronization is a common problem when two asynchronous systems are connected, and careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. The considerations for proper operation are discussed below.
1.Unsynchronized Reading of Receive Byte Registers:
When reading receive byte registers, RXH, RXM, or RXL, the host programmer should use interrupts or poll the RXDF flag which indicates that data is available. This guarantees that the data in the receive byte registers will be stable.
2.Overwriting Transmit Byte Registers:
The host programmer should not write to the transmit byte registers, TXH, TXM, or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the DSP will read stable data when it reads the HRX register.
3.Synchronization of Status Bits from DSP to Host:
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the HI and read by the host processor. The host can read these status bits very quickly without regard to the clock rate used by the DSP, but there is a chance that the state of the bit could be changing during the read operation. This possible change is generally not a system problem, since the bit will be read correctly in the next pass of any host polling routine.
However, if the host holds HEN for the minimum assertion time plus x clock cycles (see “Host Port Usage Considerations” in the DSP56002 Technical Data
Sheet (DSP56002/D) for the minimum number of cycles), the status data is guaranteed to be stable. The x clock cycles are used to synchronize the HEN signal and block internal updates of the status bits. There is no other minimum
HEN assertion time relationship to DSP clocks. There is a minimum HEN deassertion time so that the blocking latch can be updated if the host is in a tight polling loop. This minimum time only applies to reading status bits.
The only potential problem with the host processor’s reading of status bits would be its reading HF3 and HF2 as an encoded pair. For example, if the DSP changes HF3 and HF2 from “00” to “11”, there is a small possibility that the host could read the bits during the transition and receive “01” or “10” instead of “11”.
If the combination of HF3 and HF2 has significance, the host processor could
5 - 66 PORT B MOTOROLA
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