Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

GENERAL-PURPOSE I/O (PORT C)

6.2GENERAL-PURPOSE I/O (PORT C)

When it is configured as GPIO, Port C can be viewed as nine I/O pins (see Figure 6-2), which are controlled by three memory-mapped registers. These registers are the Port C control register (PCC), Port C data direction register (PCDDR), and Port C data register (PCD) (see Figure 6-3).

Figure 6-2 Port C GPIO Control

Reset clears PCC and PCDDR to configure Port C as general-purpose I/O with all nine pins as inputs. (External circuitry connected to these pins may need pullups until the pins are configured for operation.) Each Port C pin may be individually programmed as a gener- al-purpose I/O pin or as a dedicated on-chip peripheral pin under software control. Pin selection between general-purpose I/O and SCI or SSI is made by setting the appropriate PCC bit (memory location X:$FFE1) to zero for general-purpose I/O or to one for serial interface.

The PCDDR (memory location X:$FFE3) programs each pin corresponding to a bit in the PCD

(memory location X:$FFE5) as an input pin (if PCDDR=0) or as an output pin (if PCDDR=1).

If a pin is configured as a GPIO input (as shown in Figure 6-4) and the processor reads the PCD, the processor sees the logic level on the pin. If the processor writes to the PCD, the data is latched there, but does not appear on the pin because the buffer is in the high-impedance state.

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

GENERAL-PURPOSE I/O (PORT C)