Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

PLL PINS

2.3.4Debug Request Input (DR)

The debug request input (DR) allows the user to enter the debug mode of operation from the external command controller. When DR is asserted, it causes the DSP to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the DSI line. While in debug mode, the DR pin lets the user reset the OnCE controller by asserting it and deasserting it after receiving an acknowledge. It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost. Asserting DR when the DSP is in the WAIT or the STOP state, and keeping it asserted until an acknowledge pulse in the DSP is produced, sends the DSP into the debug mode. After receiving the acknowledge, DR must be deasserted before sending the first OnCE command. For more information, see Section 10.6 METHODS OF ENTERING THE DEBUG MODE in the DSP56000 Family Manual (DSP56KFAMUM/AD).

2.4PLL PINS

The following pins are dedicated to the PLL operation:

•Analog PLL Circuit Power (PVCC) — The Vcc input is dedicated to the analog PLL circuits. The voltage should be well regulated and the pin should be pro-

vided with an extremely low impedance path to the Vcc power rail. PVcc should be bypassed to PGND by a 0.1 F capacitor located as close as possible to the

chip package.

•Analog PLL Circuit Ground (PGND) — This GND input is dedicated to the an-

alog PLL circuits. The pin should be provided with an extremely low impedance path to ground. PVcc should be bypassed to PGND by a 0.1 F capacitor locat-

ed as close as possible to the chip package.

•CKOUT Power (CLVCC) — This input acts as VCC for the CKOUT output. The voltage should be well regulated and the pin should be provided with an ex-

tremely low impedance path to the VCC power rail. CLVCC should be bypassed to CLGND by a 0.1 F capacitor located as close as possible to the chip

package.

•CKOUT Ground (CLGND) — This input acts as GND for the CKOUT output.

The pin should be provided with an extremely low impedance path to ground.

CLVCC should be bypassed to CLGND by a 0.1 F capacitor located as close as possible to the chip package.

•PLL Filter Capacitor (PCAP) — This input is used to connect an external capacitor needed for the PLL filter. One terminal of the capacitor is connected to

PCAP while the other terminal is connected to PVCC. The capacitor value is specified in the DSP56002 Technical Data Sheet (DSP56002/D).

MOTOROLA DSP56002 PIN DESCRIPTIONS 2 - 13

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

TIMER/EVENT COUNTER MODULE PIN

•Output Clock (CKOUT) — This output pin provides a 50% duty cycle output clock synchronized to the internal processor clock when the PLL is enabled and locked. When the PLL is disabled, the output clock at CKOUT is derived from, and has the same frequency and duty cycle as, EXTAL.

Note: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CKOUT is synchronized to EXTAL. (For information on the DSP56002’s PLL multiplication factor, see Section Section 3.6 PLL MULTIPLICATION FACTOR.

•CKOUT Polarity Control (CKP) — This input pin defines the polarity of the CKOUT clock output. Strapping CKP through a resistor to GND will make the CKOUT polarity the same as the EXTAL polarity. Strapping CKP through a resistor to Vcc will make the CKOUT polarity the inverse of the EXTAL polarity. The CKOUT clock polarity is internally latched at the end of the hardware reset, so that any changes of the CKP pin logic state after deassertion of hardware reset will not affect the CKOUT clock polarity.

•PLL Initialization Input (PINIT) — During the assertion of hardware reset, the value at the PINIT input pin is written into the PEN bit of the PLL control register.

The PEN bit enables the PLL by causing it to derive the internal clocks from the PLL VCO output. When the bit is clear, the PLL is disabled and the chip’s internal clocks are derived from the clock connected to the EXTAL pin. After hardware reset is deasserted, the PINIT pin is ignored.

•Phase and Frequency Locked (PLOCK) — The PLOCK output originates from the Phase Detector. The chip asserts PLOCK when the PLL is enabled and has locked on the proper phase and frequency of EXTAL. The PLOCK output is deasserted by the chip if the PLL is enabled and has not locked on the proper phase and frequency. PLOCK is asserted if the PLL is disabled. PLOCK is a reliable indicator of the PLL lock state only after the chip has exited the hardware reset state. During hardware reset, the PLOCK state is determined by PINIT and by the PLL lock condition.

2.5TIMER/EVENT COUNTER MODULE PIN

The bidirectional TIO pin is the pin that provides an interface to the timer/event counter module. When the TIO is used as an input, the module functions as an external event counter, or it measures external pulse width/signal period. When the TIO is used as an output, the module functions as a timer and the signal on the TIO pin is the timer pulse. When the timer module is not using the TIO pin, the TIO can act as a general purpose I/O pin.

2 - 14 DSP56002 PIN DESCRIPTIONS MOTOROLA

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