Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

PORT A TIMING

and Y: memory spaces. Although external program memory must be 24 bits, external data memory does not. Of course, this is application specific. Many systems use 16 or fewer bits for A/D and D/A conversion and, therefore, they may only need to store 16, 12, or even eight bits of data. The 24/56 bits of internal precision is usually sufficient for intermediate results. This is a cost saving feature which can reduce the number of external memory chips.

4.3PORT A TIMING

The external bus timing is defined by the operation of the address bus, data bus, and bus control pins. The transfer of data over the external data bus is synchronous with the clock. The timing A, B, and C relative to the edges of an external clock (see Figure 4-6 and Figure 4-7) are provided in the DSP56002 Advance Information Data Sheet (DSP56002/D).

This timing is essential for designing synchronous multiprocessor systems. Figure 4-6 shows the port A timing with no wait states (wait-state control is discussed in Section 4.4). One instruction cycle equals two clock cycles or four clock phases. The clock phases, which are numbered T0 – T3, are used for timing on the DSP. Figure 4-7 shows the same timing with two wait states added to the external X: memory access.

Four TW clock phases have been added because one wait state adds two T phases and

DATA OUT

Figure 4-6 Port A Bus Operation with No Wait States

MOTOROLA PORT A 4 - 9

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

PORT A TIMING

Figure 4-7 Port A Bus Operation with Two Wait States

is equivalent to repeating the T2 and T2 clock phases. The write signal is also delayed from the T1 to the T2 state when one or more wait states are added to ease interfacing to the port. Each external memory access requires the following procedure:

1.The external memory address is defined by the address bus (A0–A15) and the memory reference selects (PS, DS, and X/Y). These signals change in the first phase (T0) of the bus cycle. Since the memory reference select signals have the same timing as the address bus, they may be used as additional address lines. The address and memory reference signals are also used to generate chip-select signals for the appropriate memory chips. These chip-select signals change the memory chips from low-power standby mode to active mode and begin the read access time. This mode change allows slower memories to be used since the chip-select signals can be address based rather than read or write enable based. Read and write enable do not become active until after the address is valid. See the timing diagrams in the DSP56002 Advance Information Data Sheet (DSP56002/D) for detailed timing information.

2.When the address and memory reference signals are stable, the data transfer

4 - 10 PORT A MOTOROLA

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

PORT A TIMING

is enabled by read enable (RD) or write enable (WR). RD or WR is asserted to “qualify” the address and memory reference signals as stable and to perform the read or write data transfer. RD and WR are asserted in the second phase of the bus cycle (if there are no wait states). Read enable is typically connected to the output enable (OE) of the memory chips and simply controls the output buffers of the chip-selected memory. Write enable is connected to the write enable (WE) or write strobe (WS) of the memory chips and is the pulse that strobes data into the selected memory. For a read operation, RD is asserted and WR remains deasserted. Since write enable remains negated, a memory read operation is performed. The DSP data bus becomes an input, and the memory data bus becomes an output. For a write operation, WR is asserted and RD remains deasserted. Since read enable remains deasserted, the memory chip outputs remain in the high-impedance state even before write strobe is asserted. This state assures that the DSP and the chip-selected memory chips are not enabled onto the bus at the same time. The DSP data bus becomes an output, and the memory data bus becomes an input.

3.Wait states are inserted into the bus cycle by a wait-state counter or by asserting WT. The wait-state counter is loaded from the bus control register. If the value loaded into the wait-state counter is zero, no wait states are inserted into

the bus cycle, and RD and WR are asserted as shown in Figure 4-6. If a value W≠0 is loaded into the wait state counter, W wait states are inserted into the

bus cycle. When wait states are inserted into an external write cycle, WR is delayed from T1 to T2. The timing for the case of two wait states (W=2) is shown in Figure 4-7.

4.When RD or WR are deasserted at the start of T3 in a bus cycle, the data is latched in the destination device – i.e., when RD is deasserted, the DSP latches the data internally; when WR is deasserted, the external memory latches the data on the positive-going edge. The address signals remain stable until the first phase of the next external bus cycle to minimize power dissipation. The memory reference signals (PS, DS, and X/Y) are deasserted (held high) during periods of no bus activity, and the data signals are three-stated. For read-modify-write instructions such as BSET, the address and memory

reference signals remain active for the complete composite (i.e., two Icyc) instruction cycle.