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BUS ARBITRATION AND SHARED MEMORY

state logic to establish the start of an external access. BS is deasserted in T3 of each external bus cycle, signaling that the current bus cycle will complete. Since the WT signal is internally synchronized, it can be asserted asynchronously with respect to the system clock. The WT signal should only be asserted while BS is asserted. Asserting WT while BS is deasserted will give indeterminate results. However, for the number of inserted wait states to be deterministic, WT timing must satisfy setup and hold timing with respect to the negative-going edge of EXTAL. The setup and hold times are provided in the DSP56002 Advance Information Data Sheet (DSP56002/D). The timing of WR is controlled by the BCR and is independent of WT. The minimum number of wait states that can be inserted using the WT pin is two. The BCR is still operative when using BS and WT and defines the minimum number of wait states that are inserted. Table 4-2 summarizes the effect of the BCR and WT pin on the number of wait states generated.

4.7BUS ARBITRATION AND SHARED MEMORY

The DSP56002 has five pins that control port A. They are bus needed (BN), bus request (BR), bus grant (BG), bus strobe (BS) and bus wait (WT) and they are described in SECTION 2 DSP56002 PIN DESCRIPTIONS.

The bus control signals provide the means to connect additional bus masters (which may be additional DSPs, microprocessors, direct memory access (DMA) controllers, etc.) to the port A bus. They work together to arbitrate and determine what device gets access to the bus.

If an external device has requested the external bus by asserting the BR input, and the DSP has granted the bus by asserting BG, the DSP will continue to process as long as it requires no external bus accesses itself. If the DSP does require an external access but is not the bus master, it will stop processing and remain in wait states until it regains bus ownership. The BN pin will have been asserted, and an external device may use BN to help “arbitrate”, or decide when to return bus ownership to the chip.

Four examples of bus arbitration will be described later in this section: 1) bus arbitration using only BR and BG with internal control, 2) bus arbitration using BN, BR, and BG with

external control, 3) bus arbitration using BR, BG and WT, BS with no overhead, and 4) signaling using semaphores.

The BR input allows an external device to request and be given control of the external bus while the DSP continues internal operations using internal memory spaces. This allows a bus controller to arbitrate a multiple bus-master system. (A bus master can issue addresses on the bus; a bus slave can respond to addresses on the bus. A single device can be both a master and a slave, but can only be one or the other at any given time.)

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BUS ARBITRATION AND SHARED MEMORY

BR

BG

Figure 4-11 Bus Request/Bus Grant Sequence

Before BR is asserted, all port A signals are driven. When BRis asserted (see Figure 4-11), the DSP will assert BG after the current external access cycle completes and will simultaneously three-state (high-impedance) the port A signals (see the DSP56002 Technical Data Sheet (DSP56002/D) for exact timing of BR and BG). The bus is then available to whatever external device has bus mastership. The external device will return bus mastership to the DSP by deasserting BR. After the DSP completes the current cycle (an internally executed instruction with or without wait states), BG will be deasserted. When BG is deasserted, the A0-A15, PS, DS, X/Y, and RD, WR lines will be driven. However, the data lines will remain in three-state. All signals are now ready for a normal external access.

During the wait state (see Section 7 in the DSP56000 Family Manual), the BR and BG circuits remain active. However, the port is inactive - the control signals are deasserted, the data signals are inputs, and the address signals remain as the last address read or written. When BR is asserted, all signals are three-stated (high impedance). Table 4-3 shows the status of BR and BG during the wait state.

Table 4-3 BR and BG During WAIT

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BUS ARBITRATION AND SHARED MEMORY

4.7.1Bus Arbitration Using Only BR and BG With Internal Control

Perhaps the simplest example of a shared memory system using a DSP56002 is shown in Figure 4-12. The bus arbitration is performed within the DSP#2 by using software. DSP#2 controls all bus operations by using I/O pin OUT2 to three-state its own port A and by never accessing port A without first calling the subroutine that arbitrates the bus. When the DSP#2 needs to use external memory, it uses I/O pin OUT1 to request bus access and I/O pin IN1 to read bus grant. DSP#1 does not need any extra code for bus arbitration since the BR and BG hardware handles its bus arbitration automatically. The protocol for bus arbitration is as follows:

At reset: DSP#2 sets OUT2=0 (BR#2=0) and OUT1=1 (BR#1=1), which gives DSP#1 access to the bus and suspends DSP#2 bus access.

When DSP#2 wants control of the memory, the following steps are performed (see Figure 4-13):

1.DSP# 2 sets OUT1=0 (BR#1=0).

2.DSP# 2 waits for IN1=0 (BG#1=0 and DSP#1 off the bus).

3.DSP#2 sets OUT2=1 (BR#2=1 to let DSP#2 control the bus).

4.DSP#2 accesses the bus for block transfers, etc. at full speed.

5.To release the bus, DSP#2 sets OUT2=0 (BR#2=0) after the last external access.

6.DSP#2 then sets OUT1=1 (BR#1=1) to return control of the bus to DSP#1.

7.DSP#1 then acknowledges mastership by deasserting BG#1.

4.7.2Bus Arbitration Using BN, BR, and BG With External Control

Figure 4-14 can be implemented with external bus arbitration logic, which will save processing capacity on the DSPs and can make bus access much faster at a cost of additional hardware. The bus arbitration logic takes control of the external bus by deasserting an enable signal (E1, E2, and E3) to all DSPs, which will then acknowledge by granting the bus (BG=0). When a DSP (DSP#1 in Figure 4-14) needs the bus, it will enter the WAIT state with BN asserted. If DSP#1 has highest priority, the arbitration logic grants the bus to DSP#1 by asserting E1 (E2 for DSP#2; E3 for DSP#3) to let the DSP know that it can have the bus. DSP#1 will then deassert BG to tell the arbiter it has taken control of the bus. When the DSP no longer needs to make an external access it will deassert BN and the arbiter deasserts E1, after which the DSP deasserts BG.

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BUS ARBITRATION AND SHARED MEMORY

BUS ARBITRATION LOGIC WITH PRIORITY ENCODER

Figure 4-14 Bus Arbitration Using BN, BR, and BG with External Control

4.7.3Bus Arbitration Using BR and BG, and WT and BS With No Overhead

By using the circuit shown in Figure 4-15, two DSPs can share memory with hardware arbitration that requires no software on the part of the DSPs. The protocol for bus arbitration in Figure 4-15 is as follows:

At RESET assume DSP#1 is not making external accesses so that BR#2 is deasserted. Hence, BG of DSP#2 is deasserted, which three-states the buffers, giving DSP#2 control of the memory.

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