Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

GENERAL PURPOSE I/O CONFIGURATION

5.2GENERAL PURPOSE I/O CONFIGURATION

When it is configured as general-purpose I/O, Port B acts as three memory-mapped registers (see Figure 5-2) that control 15 I/O pins (see Figure 5-3). They are the Port B control register (PBC), Port B data direction register (PBDDR), and Port B data register (PBD).

The software and hardware resets clear the PBC and PBDDR, which configures Port B as general-purpose I/O, with all 15 pins as inputs. (External circuitry connected to these pins may need pullups until the pins are configured for operation.)

To select between general purpose I/O and the HI, set PBC bits 0 and 1 as shown in Figure 5-2. Use the PBDDR to determine whether the corresponding bit in the PBD shall be an input pin (bit is set to zero) or an output pin (bit is set to one).

If a pin is configured as a GPIO input (as shown in Figure 5-4) and the processor reads the PBD, the processor sees the logic level on the pin. If the processor writes to the PBD, the data is latched there, but does not appear on the pin because the buffer is in the highimpedance state.

01 Host Interface

10 Host Interface (with HACK pin as GPIO)

Figure 5-2 Parallel Port B Registers

5 - 4 PORT B MOTOROLA

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