Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

PORT A WAIT STATES

Figure 4-8 shows an example of mixing different memory speeds and memory-mapped peripherals in different address spaces. The internal memory uses no wait states, X: memory uses two wait states, Y: memory uses four wait states, P: memory uses five wait states, and the analog converters use 14 wait states. Controlling five different devices at five different speeds requires only one additional logic package. Half the gates in that package are used to map the analog converters to the top 64 memory locations in Y: memory.

4.4PORT A WAIT STATES

The DSP56002 features two methods to allow the user to accommodate slow memory by changing the port A bus timing. The first method uses the bus control register (BCR), which allows a fixed number of wait states to be inserted in a given memory access to all locations in each of the four memory spaces: X, Y, P, and I/O. The second method uses the bus strobe (BS) and bus wait (WT) facility, which allows an external device to insert an arbitrary number of wait states when accessing either a single location or multiple locations of external memory or I/O space. Wait states are executed until the external device releases the DSP to finish the external memory cycle.

Table 4-2 Wait State Control

4.5BUS CONTROL REGISTER (BCR)

The BCR determines the expansion bus timing by controlling the timing of the bus interface signals, RD and WR, and the data output lines. It is a memory mapped register located at X:$FFFE. Each of the memory spaces in Figure 4-9 (X data, Y data, program data, and I/O) has its own 4-bit BCR, which can be programmed for inserting up to 15 wait states (each wait state adds one-half instruction cycle to each memory access – i.e.,

50 ns for a 20-Mhz clock). In this way, external bus timing can be tailored to match the speed requirements of the different memory spaces. On processor reset, the BCR is preset to all ones (15 wait states). This allows slow memory to be used for boot strapping. The BCR needs to be set appropriately for the memory being used or the processor will insert 15 wait states between each memory fetch and cause the DSP to run slow.

MOTOROLA PORT A 4 - 13

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

BUS CONTROL REGISTER (BCR)

* Zero to 15 wait states can be inserted into each external memory access.

Figure 4-9 Bus Control Register

Figure 4-9 illustrates which of the four BCR subregisters affect which external memory space. All the internal peripheral devices are memory mapped, and their control registers reside between X:$FFC0 and X:$FFFF.

To load the BCR the way it is shown in Figure 4-8, execute a “MOVEP #$48AD, X:$FFFE” instruction. Or, change the individual bits in one of the four subregisters by using the BSET and BCLR instructions which are detailed in the DSP56000 Family Manual, SECTION 6 and APPENDIX A.

Figure 4-8 shows an example of mixing different memory speeds and memory-mapped peripherals in different address spaces. The internal memory uses no wait states, X: memory uses two wait states, Y: memory uses four wait states, P: memory uses five wait states, and the analog converters use 14 wait states. Controlling five different devices at five different speeds requires only one additional logic package. Half the gates in that package are used to map the analog converters to the top 64 memory locations in Y: memory.

4 - 14 PORT A MOTOROLA

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