Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

HOST INTERFACE (HI)

;**************************************************

;This routine loads from the Host Interface.

;MC:MB:MA=100 - reserved

;MC:MB:MA=101 - Host

Figure 5-31 Bootstrap Code Fragment

Port B as the HI and the first JCLR looks for a flag (HF0) to indicate an early termination of the download. The second JCLR instruction causes the DSP to wait for a complete word to be received and then a MOVEP moves the data from the HI to memory.

5.3.6.2.4DSP to Host Data Transfer

Data is transferred from the DSP to the host processor in a similar manner as from the host processor to the DSP. Figure 5-32 shows the bits in the status registers (ISR and HSR) and control registers (ICR and HCR) used by the host processor and DSP CPU, respectively. The DSP CPU (see Figure 5-33) can poll the HTDE bit in the HSR (1) to see when it can send data to the host, or it can use interrupts enabled by the HTIE bit in the HCR (2). If HTIE=1 and interrupts are enabled, exception processing begins at interrupt vector P:$0022 (3). The interrupt routine should write data to the HTX (4), which will clear HTDE in the HSR. From the host’s viewpoint, (5) reading the RXL clears RXDF in the ISR. When RXDF=0 and HTDE=0 (6) the contents of the HTX will be transferred to the receive byte registers (RXH:RXM:RXL). This transfer sets RXDF in the ISR (7), which the host processor can poll to see if data is available or, if the RREQ bit in the ICR is set, the HI will interrupt the host processor with HREQ (8).

The code shown in Figure 5-34 is essentially the same as the MAIN PROGRAM in Figure 5-25 except that, since this code will transmit instead of receive data, the HTIE bit is set in the HCR instead of the HRIE bit.

The transmit routine used by the code in Figure 5-34 is shown in Figure 5-35. The interrupt vector contains a JSR, which makes it a long interrupt. The code sends a fixed test pattern

5 - 52 PORT B MOTOROLA

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MOTOROLA