Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

DSP56002 OPERATING MODE REGISTER (OMR)

3.2.2X Data Memory

The on-chip X data RAM is a 24-bit-wide, static internal memory occupying the lowest 256 locations (0–255) in X memory space. The on-chip X data ROM occupies locations 256– 511 in the X data memory space and is controlled by the DE bit in the OMR. (See the explanation of the DE bit in Section 3.3.2 Data ROM Enable (Bit 2). Also, see Figure 3- 1.)The on-chip peripheral registers occupy the top 64 locations of the X data memory ($FFC0–$FFFF). The 16-bit addresses are received from the XAB, and 24-bit data transfers to the data ALU occur on the XDB. The X memory may be expanded to 64K off-chip.

3.2.3Y Data Memory

The on-chip Y data RAM is a 24-bit-wide internal static memory occupying the lowest 256 locations (0–255) in the Y memory space. The on-chip Y data ROM occupies locations 256–511 in Y data memory space and is controlled by the DE and YD bits in the OMR. (See the explanations of the DE and YD bits in Sections Section 3.3.2 Data ROM Enable (Bit 2) and Section 3.3.3 Internal Y Memory Disable Bit (Bit 3), respectively. Also, see Figure 3-1.) The 16-bit addresses are received from the YAB, and 24-bit data transfers to the data ALU occur on the YDB. Y memory may be expanded to 64K off-chip.

Note: The off-chip peripheral registers should be mapped into the top 64 locations ($FFC0– $FFFF) to take advantage of the move peripheral data (MOVEP) instruction.

3.3DSP56002 OPERATING MODE REGISTER (OMR)

Operating modes determine the memory maps for program and data memories, and the start-up procedure when the DSP leaves the reset state. The processor samples the MODA, MODB, and MODC pins as it leaves the reset state, establishes the initial operating mode, and writes the operating mode information to the Operating Mode Register. When the processor leaves the reset state, the MODA and MODB pins become general-purpose interrupt pins, IRQA and IRQB, respectively, and the MODC pin becomes the nonmaskable interrupt pin NMI.

The OMR is a 24-bit register (only six bits are defined) that controls the current operating mode of the processor. It is located in the DSP56002’s Program Control Unit (described in Section 5 of the DSP56000 Family Manual). The OMR bits are only affected by processor reset and by the ANDI, ORI, MOVEC, BSET, BCLR, and BCHG instructions, which directly reference the OMR. The OMR format for the DSP56002 is shown in Figure 3-2 OMR Format.

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

DSP56002 OPERATING MODE REGISTER (OMR)

NOTE: Addresses $FFC0–$FFFF in X data memory are NOT available externally

Figure 3-1 DSP56002 Memory Maps

MOTOROLA MEMORY MODULES AND OPERATING MODES 3 - 5

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